SN74ALVCH16823

ACTIVE

18-Bit Bus-Interface Flip-Flop With 3-State Outputs

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18-Bit Bus-Interface Flip-Flop With 3-State Outputs

SN74ALVCH16823

ACTIVE

Product details

Parameters

Number of channels (#) 18 Technology Family ALVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 3.6 Input type Standard CMOS Output type 3-State Clock Frequency (Max) (MHz) 150 IOL (Max) (mA) 24 IOH (Max) (mA) -24 ICC (Max) (uA) 40 Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Bus-hold open-in-new Find other D-type flip-flop

Package | Pins | Size

SSOP (DL) 56 191 mm² 18.42 x 10.35 TSSOP (DGG) 56 113 mm² 14 x 8.1 TVSOP (DGV) 56 50 mm² 4.4 x 11.3 open-in-new Find other D-type flip-flop

Features

  • Member of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

Widebus, EPIC are trademarks of Texas Instruments.

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Description

This 18-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16823 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The SN74ALVCH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, thus latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the clock.

A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

The output-enable (OE) input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16823 is characterized for operation from -40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet SN74ALVCH16823 datasheet (Rev. F) Mar. 31, 2005
* Errata Datasheet Errata for SN74ALVCH16823 Device Type Jun. 13, 2006
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) Sep. 17, 2018
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) Aug. 01, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) Sep. 08, 1999
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 Aug. 03, 1998
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) May 13, 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

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Design tools & simulation

SIMULATION MODEL Download
SCEJ218.ZIP (100 KB) - HSpice Model
SIMULATION MODEL Download
SCEM039B.ZIP (59 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
SSOP (DL) 56 View options
TSSOP (DGG) 56 View options
TVSOP (DGV) 56 View options

Ordering & quality

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