SN74ALVCH373

ACTIVE

Octal Transparent D-Type Latch with 3-State Outputs

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Octal Transparent D-Type Latch with 3-State Outputs

SN74ALVCH373

ACTIVE

Product details

Parameters

Technology Family ALVC Input type Standard CMOS Output type 3-State VCC (Min) (V) 1.65 VCC (Max) (V) 3.6 Channels (#) 8 Clock Frequency (Max) (MHz) 150 ICC (uA) 20 IOL (Max) (mA) 24 IOH (Max) (mA) -24 Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Bus hold Rating Catalog open-in-new Find other D-type latch

Package | Pins | Size

SOIC (DW) 20 132 mm² 12.8 x 10.3 TSSOP (PW) 20 42 mm² 6.5 x 6.4 TVSOP (DGV) 20 32 mm² 5 x 6.4 open-in-new Find other D-type latch

Features

  • Operates From 1.65 V to 3.6 V
  • Max tpd of 3.3 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

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Description

This octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

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Technical documentation

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Type Title Date
* Datasheet SN74ALVCH373 datasheet (Rev. H) Sep. 02, 2004
Application notes An Overview of Bus-Hold Circuit and the Applications (Rev. B) Sep. 17, 2018
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
User guides ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) Aug. 01, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application notes 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application notes Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) Sep. 08, 1999
Application notes TI SN74ALVC16835 Component Specification Analysis for PC100 Aug. 03, 1998
Application notes Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) May 13, 1998
Application notes Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCEM219.ZIP (54 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
BGA MICROSTAR JUNIOR (ZQN) 20 View options
SOIC (DW) 20 View options
TSSOP (PW) 20 View options
TVSOP (DGV) 20 View options

Ordering & quality

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