SN74AUC74

ACTIVE

Dual Positive-Edge-Triggered D-Type Flip-Flops with Clear and Preset

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Product details

Parameters

Channels (#) 2 Technology Family AUC VCC (Min) (V) 0.8 VCC (Max) (V) 2.7 Input type Standard CMOS Output type Push-Pull Clock Frequency (Max) (MHz) 350 IOL (Max) (mA) 9 IOH (Max) (mA) -9 ICC (Max) (uA) 10 Features Balanced outputs, Ultra high speed (tpd <5ns), Over-voltage tolerant inputs, Partial power down (Ioff) open-in-new Find other D-type flip-flop

Package | Pins | Size

VQFN (RGY) 14 12 mm² 3.5 x 3.5 open-in-new Find other D-type flip-flop

Features

  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial-Power-Down Mode Operation
  • Sub-1-V Operable
  • Max tpd of 1.8 ns at 1.8 V
  • Low Power Consumption, 10-µ Max ICC
  • ±8-mA Output Drive at 1.8 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

open-in-new Find other D-type flip-flop

Description

This dual positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, the CLR input overrides the PRE input when they are both low.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

open-in-new Find other D-type flip-flop
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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SN74AUC74 datasheet (Rev. A) Mar. 21, 2005
Selection guide Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note How to Select Little Logic (Rev. A) Jul. 26, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus Devices Mar. 21, 2003
User guide AUC Data Book, January 2003 (Rev. A) Jan. 01, 2003
Application note Texas Instruments Little Logic Application Report Nov. 01, 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS Mar. 27, 2002
More literature AUC Product Brochure (Rev. A) Mar. 18, 2002

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
20
Description
Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic and translation devices with included dual supply support
  • Board has 9 sections that can be broken apart for a smaller form factor

Design tools & simulation

SIMULATION MODEL Download
SCEM365.ZIP (53 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
VQFN (RGY) 14 View options

Ordering & quality

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  • MTBF/FIT estimates
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  • Ongoing reliability monitoring

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