SN74AVC16722 22-Bit Flip-Flop With 3-State Outputs | TI.com

SN74AVC16722
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22-Bit Flip-Flop With 3-State Outputs

22-Bit Flip-Flop With 3-State Outputs - SN74AVC16722
Datasheet
 

Description

A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOCTM ) Circuitry Technology and Applications, literature number SCEA009.

This 22-bit flip-flop is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation.

The 22 flip-flops of the SN74AVC16722 are edge-triggered D-type flip-flops with clock-enable (CLKEN\) input. On the positive transition of the clock (CLK) input, the device stores data into the flip-flops if CLKEN\ is low. If CLKEN\ is high, no data is stored.

A buffered output-enable (OE\) input places the 22 outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74AVC16722 is characterized for operation from -40°C to 85°C.

Features

  • Member of the Texas Instruments WidebusTM Family
  • EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process
  • DOCTM (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
  • Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class I
  • Packaged in Thin Shrink Small-Outline Package

    DOC, EPIC, and Widebus are trademarks of Texas Instruments.

Parametrics

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Part number Order Technology Family Input type Output type VCC (Min) (V) VCC (Max) (V) Channels (#) Clock Frequency (Max) (MHz) ICC (uA) IOL (Max) (mA) IOH (Max) (mA) Features Rating Package Group
SN74AVC16722 Order now AVC     Standard CMOS     3-State     1.4     3.6     22     175     40     12     -12     Balanced outputs
Very high speed (tpd 5-10ns)
Over-voltage tolerant inputs
Partial power down (Ioff)    
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