SN74F377A

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Octal D-Type Flip-Flop With Clock Enable

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Product details

Parameters

Technology Family F Input type Bipolar Output type Push-Pull VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Channels (#) 8 Clock Frequency (Max) (MHz) 110 ICC (uA) 90000 IOL (Max) (mA) 20 IOH (Max) (mA) -1 Features Very high speed (tpd 5-10ns) Rating Catalog open-in-new Find other D-type flip-flop

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 open-in-new Find other D-type flip-flop

Features

  • Contains Eight D-Type Flip-Flops With Single-Rail Outputs
  • Clock Enable Latched to Avoid False Clocking
  • Applications Include:
  • Buffer/Storage Registers
  • Shift Registers
  • Pattern Generators
  • Buffered Common Enable Input
  • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

 

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Description

The SN74F377A is a monolithic, positive-edge-triggered, octal, D-type flip-flop with clock enable inputs. The SN74F377A features a latched clock enable () input.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if is low. Clock triggering occurs at a particular voltage level and is not directly related to the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the input.

The SN74F377A is characterized for operation from 0°C to 70°C.

 

 

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet Octal D-Type Flip-Flop With Clock Enable datasheet (Rev. D) Oct. 01, 1993
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 20 View options
SOIC (DW) 20 View options

Ordering & quality

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