SN74F574

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Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs

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Product details

Parameters

Technology Family F Input type Bipolar Output type 3-State VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Channels (#) 8 Clock Frequency (Max) (MHz) 100 ICC (uA) 86000 IOL (Max) (mA) 24 IOH (Max) (mA) -3 Features Very high speed (tpd 5-10ns) Rating Catalog open-in-new Find other D-type flip-flop

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 SOP (NS) 20 98 mm² 12.6 x 7.8 open-in-new Find other D-type flip-flop

Features

  • Eight D-Type Flip-Flops in a Single Package
  • 3-State Bus-Driving True Outputs
  • Full Parallel Access for Loading
  • Buffered Control Inputs
  • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

 

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Description

This 8-bit flip-flop features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight flip-flops of the SN74F574 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs will be set to the logic levels that were set up at the data (D) inputs.

A buffered output enable input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

The output enable does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN74F574 is characterized for operation from 0°C to 70°C.

 

 

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet Octal Edge-Triggered D-Type Flip-Flop With 3-State Outputs datasheet (Rev. A) Oct. 01, 1993
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SDFM012.ZIP (8 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 20 View options
SO (NS) 20 View options
SOIC (DW) 20 View options

Ordering & quality

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