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SN74HC03

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4-ch, 2-input, 2-V to 6-V NAND gates with open-drain outputs

Data sheet
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4-ch, 2-input, 2-V to 6-V NAND gates with open-drain outputs

SN74HC03

ACTIVE
Data sheet Order now

Product details

Parameters

Technology Family HC VCC (Min) (V) 2 VCC (Max) (V) 6 Channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 5.2 IOH (Max) (mA) 0 Input type Standard CMOS Output type Open-Drain Features High speed (tpd 10- 50ns) Data rate (Max) (Mbps) 28 Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other NAND gate

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other NAND gate

Features

  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive Up to 10 LSTTL Loads
  • Low Power Consumption, 20-µA Max ICC
  • Typical tpd = 8 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max

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Description

The ’HC03 devices contain four independent 2-input NAND gates. They perform the Boolean function Y = (A • B)\ or Y = A\ + B\ in positive logic. The open-drain outputs require pullup resistors to perform correctly. They may be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions.

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Technical documentation

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Type Title Date
* Datasheet SN54HC03, SN74HC03 datasheet (Rev. E) Nov. 19, 2003
Technical article How to keep your motor running safely Jun. 04, 2020
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
View details

Design tools & simulation

SIMULATION MODEL Download
SCLM233.ZIP (6 KB) - PSpice Model

Reference designs

REFERENCE DESIGNS Download
Industrial Servo Drive and AC Inverter Drive Reference Design
TIDM-SERVODRIVE — The DesignDRIVE Development Kit is a reference design for a complete industrial drive directly connecting to a three phase ACI or PMSM motor. Many drive topologies can be created from the combined control, power and communications technologies included on this single platform.  Includes (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Data Concentrator Reference Design for Smaller AMI Networks Reduces Infrastructure Cost
TIDM-MINI-DC — The TIDM-MINI-DC reference design implements a light-weight powerline communication (PLC) data concentrator (DC) solution integrated with an Ethernet repeater feature. A power grid network is static, which means that once end-nodes are installed the number of nodes to be supported by a DC is fixed (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options
TSSOP (PW) 14 View options

Ordering & quality

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