SN74HC03 Quadruple 2-Input Positive-NAND Gates With Open-Drain Outputs | TI.com

SN74HC03
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Quadruple 2-Input Positive-NAND Gates With Open-Drain Outputs

Quadruple 2-Input Positive-NAND Gates With Open-Drain Outputs - SN74HC03
Datasheet
SN54HC03, SN74HC03 datasheet (Rev. E)
 

Description

The ’HC03 devices contain four independent 2-input NAND gates. They perform the Boolean function Y = (A • B)\ or Y = A\ + B\ in positive logic. The open-drain outputs require pullup resistors to perform correctly. They may be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions.

Features

  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive Up to 10 LSTTL Loads
  • Low Power Consumption, 20-µA Max ICC
  • Typical tpd = 8 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max

Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) Inputs per channel IOL (Max) (mA) IOH (Max) (mA) Input type Output type Features Rating Data rate (Max) (Mbps) Operating temperature range (C) Package size: mm2:W x L (PKG) Package Group
SN74HC03 Order now HC     2     6     4     2     5.2     0     Standard CMOS     Open-Drain     High Speed (tpd 10-50ns)     Catalog     28     -40 to 85     14PDIP: 181 mm2: 9.4 x 19.3 (PDIP | 14)
14SO: 80 mm2: 7.8 x 10.2 (SO | 14)
14SOIC: 52 mm2: 6 x 8.65 (SOIC | 14)
14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14)    		 PDIP | 14
SOIC | 14
SO | 14
TSSOP | 14    
SN54HC03 Samples not available HC     2     6     4     2     5.2     -5.2     Standard CMOS     Open-Drain     High Speed (tpd 10-50ns)     Military     28     -55 to 125     14CDIP: 130 mm2: 6.67 x 19.56 (CDIP | 14)
20LCCC: 79 mm2: 8.89 x 8.89 (LCCC | 20)    		 CDIP | 14
LCCC | 20