The SN74HC165 is an 8-bit parallel-load shift register that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SN74HC165 also features a clock-inhibit (CLK INH) function and a complementary serial (QH) output.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
|Part number||Order||Technology Family||VCC (Min) (V)||VCC (Max) (V)||Voltage (Nom) (V)||F @ nom voltage (Max) (MHz)||ICC @ nom voltage (Max) (mA)||tpd @ nom Voltage (Max) (ns)||IOL (Max) (mA)||IOH (Max) (mA)||3-state output||Rating||Operating temperature range (C)|
||HC||2||6||5||28||0.08||38||5.2||-5.2||No||Automotive||-40 to 125|
|SN54HC165||Samples not available||HC||2||6||6||28||0.08||38||5.2||-5.2||No||Military||-55 to 125|
||HC||2||6||6||28||0.08||38||5.2||-5.2||No||Catalog||-40 to 125|
|SN74HC165-EP||Samples not available||HC||2||6||6||28||0.08||38||5.2||-5.2||No||HiRel Enhanced Product||-40 to 125|