SN74HC165-Q1

ACTIVE

Automotive Catalog 8-Bit Parallel-Load Shift Registers

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Automotive Catalog 8-Bit Parallel-Load Shift Registers

SN74HC165-Q1

ACTIVE

Product details

Parameters

Bits (#) 8 Technology Family HC VCC (Min) (V) 2 VCC (Max) (V) 6 Input type CMOS Output type CMOS IOL (Max) (mA) 5.2 IOH (Max) (mA) -5.2 open-in-new Find other Shift register

Package | Pins | Size

SOIC (D) 16 59 mm² 9.9 x 6 TSSOP (PW) 16 22 mm² 4.4 x 5 open-in-new Find other Shift register

Features

  • Qualified for Automotive Applications
  • ESD Protection Exceeds 1500 V Per MIL-STD-883, Method 3015; Exceeds 200 V
    Using Machine Model (C = 200 pF, R = 0)
  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 13 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Complementary Outputs
  • Direct Overriding Load (Data) Inputs
  • Gated Clock Inputs
  • Parallel-to-Serial Data Conversion

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Description

The SN74HC165 is an 8-bit parallel-load shift register that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SN74HC165 also features a clock-inhibit (CLK INH) function and a complementary serial (QH) output.

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 17
Type Title Date
* Datasheet 8-Bit Parallel-Load Shift Register datasheet (Rev. A) Apr. 15, 2008
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
More literature Automotive Logic Devices Brochure Aug. 27, 2014
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
SOIC (D) 16 View options
TSSOP (PW) 16 View options

Ordering & quality

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