These devices are positive-edge-triggered octal D-type flip-flops with an enable input. The HC377 devices are similar to the HC273 devices, but feature a latched clock-enable (CLKEN)\ input instead of a common clear.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse, if CLKEN\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN\.
Part number | Order | Technology Family | Input type | Output type | VCC (Min) (V) | VCC (Max) (V) | Channels (#) | Clock Frequency (Max) (MHz) | ICC (uA) | IOL (Max) (mA) | IOH (Max) (mA) | Features | Rating | Package Group |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SN74HC377 |
|
HC | Standard CMOS | Push-Pull | 2 | 6 | 8 | 28 | 80 | 5.2 | -5.2 |
Balanced outputs
High speed (tpd 10-50ns) Positive input clamp diode |
Catalog |
PDIP | 20
SOIC | 20 SO | 20 |
SN54HC377 | Samples not available | HC | Standard CMOS | Push-Pull | 2 | 6 | 8 | 25 | 80 | 5.2 | -5.2 |
Balanced outputs
High speed (tpd 10-50ns) Positive input clamp diode |
Military |
CDIP | 20
LCCC | 20 |