SN74HC377 Octal D-Type Flip-Flops With Clock Enable | TI.com

SN74HC377
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Octal D-Type Flip-Flops With Clock Enable

Octal D-Type Flip-Flops With Clock Enable - SN74HC377
Datasheet
SN54HC377, SN74HC377 datasheet (Rev. B)
 

Description

These devices are positive-edge-triggered octal D-type flip-flops with an enable input. The ’HC377 devices are similar to the ’HC273 devices, but feature a latched clock-enable (CLKEN)\ input instead of a common clear.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse, if CLKEN\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN\.

Features

  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 12 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Eight Flip-Flops With Single-Rail Outputs
  • Clock Enable Latched to Avoid False Clocking
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators

Parametrics

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Part number Order Technology Family Input type Output type VCC (Min) (V) VCC (Max) (V) Channels (#) Clock Frequency (Max) (MHz) ICC (uA) IOL (Max) (mA) IOH (Max) (mA) Features Rating Package Group
SN74HC377 Order now HC     Standard CMOS     Push-Pull     2     6     8     28     80     5.2     -5.2     Balanced outputs
High speed (tpd 10-50ns)
Positive input clamp diode    		 Catalog     PDIP | 20
SOIC | 20
SO | 20    
SN54HC377 Samples not available HC     Standard CMOS     Push-Pull     2     6     8     25     80     5.2     -5.2     Balanced outputs
High speed (tpd 10-50ns)
Positive input clamp diode    		 Military     CDIP | 20
LCCC | 20