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SN74HCS72

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Schmitt-trigger input dual D-type negative-edge-triggered flip-flops w/ clear and preset

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Product details

Parameters

Channels (#) 2 Technology Family HCS VCC (Min) (V) 2 VCC (Max) (V) 6 Input type Schmitt-Trigger Output type Push-Pull Clock Frequency (Max) (MHz) 45 IOL (Max) (mA) 7.8 IOH (Max) (mA) -7.8 ICC (Max) (uA) 2 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode open-in-new Find other D-type flip-flop

Package | Pins | Size

SOIC (D) 14 52 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other D-type flip-flop

Features

  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 5 V
  • Extended ambient temperature range: –40°C to +125°C, TA

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open-in-new Find other D-type flip-flop

Description

This device contains two independent D-type negative-edge-triggered flip-flops. All inputs include Schmitt-triggers, allowing for slow or noisy input signals. A low level at the preset (PRE) input sets the output high. A low level at the clear (CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the negative-going edge of the clock (CLK) pulse. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q).

open-in-new Find other D-type flip-flop
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Technical documentation

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Type Title Date
* Datasheet SN74HCS72 Schmitt-Trigger Input Dual D-Type Negative-Edge-Triggered Flip-Flops With Clear and Preset datasheet (Rev. A) Jun. 30, 2020

Design & development

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Hardware development

EVALUATION BOARD Download
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SCLM162.ZIP (250 KB) - IBIS Model
SIMULATION MODEL Download
SCLM299.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
SOIC (D) 14 View options
TSSOP (PW) 14 View options

Ordering & quality

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