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SN74HCS74

ACTIVE

Schmitt-trigger input dual D-type positive-edge-triggered flip-flops w/ clear and preset

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Data sheet

SN74HCS74

ACTIVE
Data sheet Order now

Product details

Number of channels 2 Technology family HCS Input type Schmitt-Trigger Output type Push-Pull Clock frequency (max) (MHz) 65 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Supply current (max) (µA) 2 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 125 Rating Automotive, Catalog
Number of channels 2 Technology family HCS Input type Schmitt-Trigger Output type Push-Pull Clock frequency (max) (MHz) 65 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Supply current (max) (µA) 2 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 125 Rating Automotive, Catalog
SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm) SOT-23-THN (DYY) 14 13.692 mm² (4.2 mm × 3.26 mm) WQFN (BQA) 14 7.5 mm² (3 mm × 2.5 mm)
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 6 V
  • Extended ambient temperature range: –40°C to +125°C, TA
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 6 V
  • Extended ambient temperature range: –40°C to +125°C, TA

The device contains two independent D-type positive-edge-triggered flip-flops. All inputs include Schmitt triggers, allowing for slow or noisy input signals. A low level at the preset ( PRE) input sets the output high. A low level at the clear ( CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q).

The device contains two independent D-type positive-edge-triggered flip-flops. All inputs include Schmitt triggers, allowing for slow or noisy input signals. A low level at the preset ( PRE) input sets the output high. A low level at the clear ( CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q).
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Technical documentation

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* Data sheet SN74HCS74 Schmitt-Trigger Input Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset datasheet (Rev. D) PDF | HTML Dec 7, 2021
Application brief Using Linear Interpolation to Estimate Specification Values PDF | HTML Apr 13, 2026
Application brief Simplifying Solid-State Relay Designs With Logic PDF | HTML Jan 8, 2021

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14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

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14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

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Simulation model

SN74HCS74 Behavioral SPICE Model

SCEM774.ZIP (7 KB) - PSpice model
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Simulation model

SN74HCS74 IBIS Model (Rev. B)

SCEM593B.ZIP (51 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
SOIC (D) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
SOT-23-THN (DYY) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian
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