These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the HCT373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs.
An output-enable (OE)\ input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
(OE)\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.
|Part number||Order||Technology Family||Input type||Output type||VCC (Min) (V)||VCC (Max) (V)||Channels (#)||Clock Frequency (Max) (MHz)||ICC (uA)||IOL (Max) (mA)||IOH (Max) (mA)||Rating||Package Group|
PDIP | 20
SOIC | 20
SO | 20
TSSOP | 20
|SN54HCT373||Samples not available||HCT||TTL-Compatible CMOS||3-State||4.5||5.5||8||25||160||6||-6||Military||
CDIP | 20
CFP | 20
LCCC | 20