Product details

Number of channels (#) 8 Technology Family HCT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock Frequency (Max) (MHz) 28 IOL (Max) (mA) 6 IOH (Max) (mA) -6 ICC (Max) (uA) 80 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode
Number of channels (#) 8 Technology Family HCT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock Frequency (Max) (MHz) 28 IOL (Max) (mA) 6 IOH (Max) (mA) -6 ICC (Max) (uA) 80 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode
PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 SOP (NS) 20 98 mm² 12.6 x 7.8 SSOP (DB) 20 38 mm² 5.3 x 7.2 TSSOP (PW) 20 42 mm² 6.5 x 6.4
  • Operating Voltage Range of 4.5 V to 5.5 V
  • High-Current 3-State True Outputs Can Drive Up To 15 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 22 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Inputs Are TTL-Voltage Compatible
  • Eight D-Type Flip-Flops in a Single Package
  • Full Parallel Access for Loading

  • Operating Voltage Range of 4.5 V to 5.5 V
  • High-Current 3-State True Outputs Can Drive Up To 15 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 22 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Inputs Are TTL-Voltage Compatible
  • Eight D-Type Flip-Flops in a Single Package
  • Full Parallel Access for Loading

These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight flip-flops of the ’HCT374 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.

An output-enable (OE)\ input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

(OE)\ does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight flip-flops of the ’HCT374 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.

An output-enable (OE)\ input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

(OE)\ does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

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Technical documentation

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Type Title Date
* Data sheet SN54HCT374, SN74HCT374 datasheet (Rev. D) 19 Aug 2003
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) 06 Feb 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, P, N, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
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Package Pins Download
PDIP (N) 20 View options
SO (NS) 20 View options
SOIC (DW) 20 View options
SSOP (DB) 20 View options
TSSOP (PW) 20 View options

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