Universal shift / storage registers


Product details


Bits (#) 8 Technology Family LS VCC (Min) (V) 4.75 VCC (Max) (V) 5.25 Input type TTL Output type TTL IOL (Max) (mA) 24 IOH (Max) (mA) -2.6 open-in-new Find other Shift register

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 open-in-new Find other Shift register


  • Multiplexed Inputs/Outputs Provide Improved Bit Density
  • Four Modes of Operations:
    • Hold (Store)
    • Shift Left
    • Shift Right
    • Load Data
  • Operates with Outputs Enabled or at High Z
  • 3-State Outputs Drive Bus Lines Directly
  • Can Be Cascaded for N-Bit Word Lengths
  • SN54LS323 and SN74LS323 Are Similar But Have Synchronous Clear
  • Applications:
    • Stacked or Push-Down Registers Buffer Storage, and Accumulator Registers


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These Schottky TTL eight-bit universal registers feature multiplexed inputs/outputs to achieve full eight-bit data handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both function-select lines, S0 and S1, high. This places the three-state outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. A direct overriding input is provided to clear the register whether the outputs are enabled or off.


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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet 8-Bit Universal Shift/Storage Registers datasheet Mar. 01, 1988
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Designing with the SN54/74LS123 (Rev. A) Mar. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996

Design & development

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Hardware development

document-generic User guide
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 20 View options
SOIC (DW) 20 View options

Ordering & quality

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