SN74LS378 Hex D-Type Flip-Flops with Clock Enable | TI.com

SN74LS378
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Hex D-Type Flip-Flops with Clock Enable

Hex D-Type Flip-Flops with Clock Enable - SN74LS378
Datasheet
 

Description

These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input.

These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop.

 

Features

  • 'LS377 and 'LS378 Contain Eight and Six Flip-Flops, Respectively, with Single-Rail Outputs
  • 'LS379 Contains Four Flip-Flops with Double-Rail Outputs
  • Individual Data Input to Each Flip-Flop
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators

 

Parametrics

Compare all products in D-type flip-flop Email Download to Excel
Part number Order Technology Family Input type Output type VCC (Min) (V) VCC (Max) (V) IOL (Max) (mA) IOH (Max) (mA) Rating Package Group
SN74LS378 Order now LS     TTL     TTL     4.75     5.25     8     -0.4     Catalog     PDIP | 16
SOIC | 16
SO | 16    
SN54LS378 Samples not available LS     TTL     TTL     4.75     5.25     8     -0.4     Military     CDIP | 16