These devices each contain an 8-bit D-type sorage register. The storage register has buffered ('LS594) or open-collector ('LS599) outputs. Separate clocks and direct-overriding clears are provided on both the shift and storage registers. A shift output (QH') is provided for cascading purposes.
Both the shift register and the storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one clock pulse ahead of the storage register.
|Part number||Order||Technology Family||VCC (Min) (V)||VCC (Max) (V)||Voltage (Nom) (V)||F @ nom voltage (Max) (MHz)||ICC @ nom voltage (Max) (mA)||tpd @ nom Voltage (Max) (ns)||IOL (Max) (mA)||IOH (Max) (mA)||3-state output||Rating||Operating temperature range (C)|
||LS||4.75||5.25||5||35||65||25||24||-2.6||No||Catalog||0 to 70|