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Product details

Parameters

Function Counter Bits (#) 4 Technology Family LS VCC (Min) (V) 4.75 VCC (Max) (V) 5.25 Input type TTL Output type CMOS open-in-new Find other Counter, arithmetic & parity function ICs

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 open-in-new Find other Counter, arithmetic & parity function ICs

Features

  • '90A, 'LS90 . . . Decade Counters
  • '92A, 'LS92 . . . Divide By-Twelve Counters
  • '93A, 'LS93 . . . 4-Bit Binary Counters
TYPES TYPICAL
POWER DISSIPATION
'90A 145 mW
'92A, '93A 130 mW
'LS90, 'LS92, 'LS93 45 mW
open-in-new Find other Counter, arithmetic & parity function ICs

Description

Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the '90A and 'LS90, divide-by-six for the '92A and 'LS92, and the divide-by eight for the '93A and 'LS93.

All of these counters have a gated zero reset and the '90A and 'LS90 also have gated set-to-nine inputs for use in BCD nine's complement applications.

To use their maximum count length (decade, divide-by-twelve, or four-bit binary) of these counters, the CKB input is connected to the QA output. The input count pulses are applied to CKA input and the outputs are as described in the appropriate function table. A symmetrical divide-by-ten count can be obtained from the '90A or 'LS90 counters by connecting the QD output to the CKA input and applying the input count to the CKB input which gives a divide-by-ten square wave at output QA.

open-in-new Find other Counter, arithmetic & parity function ICs
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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 11
Type Title Date
* Datasheet Decade, Divide-by-Twelve And Binary Counters datasheet (Rev. A) Mar. 01, 1988
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Designing with the SN54/74LS123 (Rev. A) Mar. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options

Ordering & quality

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