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SN74LV273A-Q1

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Automotive octal D-type flip-flops with clear

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Data sheet

SN74LV273A-Q1

ACTIVE
Data sheet Order now

Product details

Number of channels 8 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 70 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 125 Rating Automotive
Number of channels 8 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 70 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 125 Rating Automotive
VQFN (RKS) 20 11.25 mm² 4.5 x 2.5
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1:
      • 40°C to + 125°C, TA
    • Device HBM ESD Classifiaction Level 2
    • Device CDM ESD Classifcation Level C6
  • Available in wettable flank QFN (WRKS) package
  • 2 V to 5.5 V VCC operation
  • Maximum tpd of 10.5 ns at 5 V
  • Supports mixed-mode voltage operation on all ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1:
      • 40°C to + 125°C, TA
    • Device HBM ESD Classifiaction Level 2
    • Device CDM ESD Classifcation Level C6
  • Available in wettable flank QFN (WRKS) package
  • 2 V to 5.5 V VCC operation
  • Maximum tpd of 10.5 ns at 5 V
  • Supports mixed-mode voltage operation on all ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17

The SN74LV273A-Q1 device is an octal positive-edge triggered D-type flip-flop with shared direct active low clear (CLR) input and clock (CLK).

Information at the data (D) inputs meeting the setup time requirements is transferred to the (Q) outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level or transitioning from a high level to a low level, the D input has no effect at the output. Information at the data (Q) outputs can be asynchronously cleared with a low level input through the clear (CLR) pin.

The SN74LV273A-Q1 device is an octal positive-edge triggered D-type flip-flop with shared direct active low clear (CLR) input and clock (CLK).

Information at the data (D) inputs meeting the setup time requirements is transferred to the (Q) outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level or transitioning from a high level to a low level, the D input has no effect at the output. Information at the data (Q) outputs can be asynchronously cleared with a low level input through the clear (CLR) pin.
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Technical documentation

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* Data sheet SN74LV273A-Q1 Automotive Octal D-Type Flip-Flops With Clear datasheet (Rev. B) 26 Jan 2023

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74LV273A-Q1 IBIS Model

SCLM350.ZIP (44 KB) - IBIS Model
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Package Pins Download
VQFN (RKS) 20 View options

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