SN74LV374A

ACTIVE

Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs

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Product details

Parameters

Number of channels (#) 8 Technology Family LV-A Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Input type Standard CMOS Output type 3-State Clock Frequency (Max) (MHz) 70 IOL (Max) (mA) 12 IOH (Max) (mA) -12 ICC (Max) (uA) 20 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) open-in-new Find other D-type flip-flops

Package | Pins | Size

SOIC (DW) 20 132 mm² 12.8 x 10.3 SOP (NS) 20 98 mm² 12.6 x 7.8 SSOP (DB) 20 38 mm² 5.3 x 7.2 TSSOP (PW) 20 42 mm² 6.5 x 6.4 open-in-new Find other D-type flip-flops

Features

  • 2-V to 5.5-V VCC Operation
  • Maximum tpd of 9.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
open-in-new Find other D-type flip-flops

Description

The SNx4LV374A devices are octal edge-triggered D-type flip-flops designed for 2-V to 5.5-V VCC operation.

open-in-new Find other D-type flip-flops
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Technical documentation

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Type Title Date
* Data sheet SNx4LV374A Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs datasheet (Rev. J) Oct. 13, 2016
Application note Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
EVALUATION BOARD Download
document-generic User guide
20
Description
Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic and translation devices with included dual supply support
  • Board has 9 sections that can be broken apart for a smaller form factor

Design tools & simulation

SIMULATION MODEL Download
SCEM142A.ZIP (15 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
SO (NS) 20 View options
SOIC (DW) 20 View options
SSOP (DB) 20 View options
TSSOP (PW) 20 View options

Ordering & quality

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  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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