SN74LV595A-Q1

ACTIVE

Automotive Catalog 8-Bit Shift Registers With 3-State Output Registers

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Automotive Catalog 8-Bit Shift Registers With 3-State Output Registers

SN74LV595A-Q1

ACTIVE

Product details

Parameters

Bits (#) 8 Technology Family LV-A VCC (Min) (V) 2 VCC (Max) (V) 5.5 Input type CMOS Output type CMOS IOL (Max) (mA) 50 IOH (Max) (mA) -50 open-in-new Find other Shift register

Package | Pins | Size

TSSOP (PW) 16 22 mm² 4.4 x 5 open-in-new Find other Shift register

Features

  • Qualified for Automotive Applications
  • Customer-Specific Configuration Control Can Be Supported
    Along With Major-Change Approval
  • 2-V to 5.5-V VCC Operation
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Voltage Operation on All Ports
  • 8-Bit Serial-In, Parallel-Out Shift
  • Ioff Supports Partial-Power-Down Mode Operation
  • Shift Register Has Direct Clear

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Description

The SN74LV595A is an 8-bit shift register designed for 2-V to 5.5-V VCC operation.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs except QH' are in the high-impedance state.

Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 3
Type Title Date
* Datasheet SN74LV595A-Q1 8-Bit Shift Register With 3-State Output Registers datasheet (Rev. D) Oct. 28, 2009
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
More literature Automotive Logic Devices Brochure Aug. 27, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
TSSOP (PW) 16 View options

Ordering & quality

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