Serial-To-Parallel Interface


Product details


Technology Family LV-A VCC (Min) (V) 3 VCC (Max) (V) 5.5 Input type CMOS Output type CMOS Voltage (Nom) (V) 3.3, 5 F @ nom voltage (Max) (MHz) 70 ICC @ nom voltage (Max) (mA) 20 Propagation delay (Max) (ns) 200, 150 IOL (Max) (mA) 40 IOH (Max) (mA) -24 3-state output No Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Shift register

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 TSSOP (PW) 20 42 mm² 6.5 x 6.4 open-in-new Find other Shift register


  • Single-Wire Serial Data Input
  • Compatible With UART Serial-Data Format
  • Up to Eight Devices (64-Bit Parallel) Can Share the Same Bus by Using Different Combinations of A0, A1, A2
  • Up to 40 mA Current Drive in Open-Collector Mode for Driving LEDs
  • Outputs Can be Configured as Open-Collector or Push-Pull
  • Internal Oscillator and Counter for Automatic Data-Rate Detection
  • Output Levels Are Referenced to VCC2 and Can Be Configured From 3 V to 12 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)

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The SN74LV8153 is a serial-to-parallel data converter. It accepts serial input data and outputs 8-bit parallel data.

The automatic data-rate detection feature of the SN74LV8153 eliminates the need for an external oscillator and helps with cost and board real-estate savings.

The OUTSEL pin is used to choose between open collector and push-pull outputs. The open-collector option is suitable when this device is used in applications such as LED interface, where high drive current is required. SOUT is the output that acknowledges reception of the serial data.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC1 through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

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Type Title Date
* Datasheet SN74LV8153 datasheet Dec. 17, 2003
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 20 View options
TSSOP (PW) 20 View options

Ordering & quality

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