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SN74LV8153

ACTIVE

Serial-To-Parallel Interface

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Data sheet

SN74LV8153

ACTIVE
Data sheet Order now

Product details

Configuration Serial-in, Parallel-out Bits (#) 8 Technology family LV-A Supply voltage (min) (V) 3 Supply voltage (max) (V) 5.5 Input type Schmitt-Trigger Output type Push-Pull Clock frequency (MHz) 0.012 IOL (max) (mA) 40 IOH (max) (mA) -24 Supply current (max) (µA) 20000 Features Over-voltage tolerant inputs, Partial power down (Ioff), Standard speed (tpd > 50ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Configuration Serial-in, Parallel-out Bits (#) 8 Technology family LV-A Supply voltage (min) (V) 3 Supply voltage (max) (V) 5.5 Input type Schmitt-Trigger Output type Push-Pull Clock frequency (MHz) 0.012 IOL (max) (mA) 40 IOH (max) (mA) -24 Supply current (max) (µA) 20000 Features Over-voltage tolerant inputs, Partial power down (Ioff), Standard speed (tpd > 50ns) Operating temperature range (°C) -40 to 85 Rating Catalog
PDIP (N) 20 228.702 mm² 24.33 x 9.4 TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Single-Wire Serial Data Input
  • Compatible With UART Serial-Data Format
  • Up to Eight Devices (64-Bit Parallel) Can Share the Same Bus by Using Different Combinations of A0, A1, A2
  • Up to 40 mA Current Drive in Open-Collector Mode for Driving LEDs
  • Outputs Can be Configured as Open-Collector or Push-Pull
  • Internal Oscillator and Counter for Automatic Data-Rate Detection
  • Output Levels Are Referenced to VCC2 and Can Be Configured From 3 V to 12 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)
  • Single-Wire Serial Data Input
  • Compatible With UART Serial-Data Format
  • Up to Eight Devices (64-Bit Parallel) Can Share the Same Bus by Using Different Combinations of A0, A1, A2
  • Up to 40 mA Current Drive in Open-Collector Mode for Driving LEDs
  • Outputs Can be Configured as Open-Collector or Push-Pull
  • Internal Oscillator and Counter for Automatic Data-Rate Detection
  • Output Levels Are Referenced to VCC2 and Can Be Configured From 3 V to 12 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)

The SN74LV8153 is a serial-to-parallel data converter. It accepts serial input data and outputs 8-bit parallel data.

The automatic data-rate detection feature of the SN74LV8153 eliminates the need for an external oscillator and helps with cost and board real-estate savings.

The OUTSEL pin is used to choose between open collector and push-pull outputs. The open-collector option is suitable when this device is used in applications such as LED interface, where high drive current is required. SOUT is the output that acknowledges reception of the serial data.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC1 through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LV8153 is a serial-to-parallel data converter. It accepts serial input data and outputs 8-bit parallel data.

The automatic data-rate detection feature of the SN74LV8153 eliminates the need for an external oscillator and helps with cost and board real-estate savings.

The OUTSEL pin is used to choose between open collector and push-pull outputs. The open-collector option is suitable when this device is used in applications such as LED interface, where high drive current is required. SOUT is the output that acknowledges reception of the serial data.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC1 through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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* Data sheet SN74LV8153 datasheet 17 Dec 2003
More literature Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
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Package Pins Download
PDIP (N) 20 View options
TSSOP (PW) 20 View options

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