SN74LVC112A Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset | TI.com

SN74LVC112A (ACTIVE) Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset

 

Description

This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation.

Features

  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.8 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 3000-V Human-Body Model
    • 200-V Machine Model
    • 1500-V Charged-Device Model

Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Bits (#) Voltage (Nom) (V) F @ nom voltage (Max) (MHz) ICC @ nom voltage (Max) (mA) tpd @ nom Voltage (Max) (ns) IOL (Max) (mA) IOH (Max) (mA) Rating
SN74LVC112A Order now LVC     2     3.6     2     3.3     100     0.01     4.8     24     -24     Catalog