SN74LVC1G57

DSBGA (YZP)

6

2 mm² .928 x 1.428

SOT-23 (DBV)

6

5 mm² 2.9 x 1.6

SOT-5X3 (DRL)

6

2 mm² 1.65 x 1.2

SOT-SC70 (DCK)

6

4 mm² 2 x 2.1

USON (DRY)

6

1 mm² 1.5 x 1

X2SON (DSF)

6

1 mm² 1 x 1

Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
- Supports Down Translation to V_CC
Max t_pd of 6.3 ns at 3.3 V
Schmitt-Triggered Inputs
Low Power Consumption, 10-µA Maximum I_CC
±24-mA Output Drive at 3.3 V
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
Available in the Texas Instruments NanoFree™ Package

Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
- Supports Down Translation to V_CC
Max t_pd of 6.3 ns at 3.3 V
Schmitt-Triggered Inputs
Low Power Consumption, 10-µA Maximum I_CC
±24-mA Output Drive at 3.3 V
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
Available in the Texas Instruments NanoFree™ Package

The SN74LVC1G57 device features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and buffer. All inputs can be connected to V_CC or GND.

This device functions as an independent gate, but because of Schmitt action, it may have different input threshold levels for positive-going (V_T+) and negative-going (V_T–) signals.

This configurable multiple-function gate is designed for 1.65-V to 5.5-V V_CC operation.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

The SN74LVC1G57 device features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and buffer. All inputs can be connected to V_CC or GND.

This device functions as an independent gate, but because of Schmitt action, it may have different input threshold levels for positive-going (V_T+) and negative-going (V_T–) signals.

This configurable multiple-function gate is designed for 1.65-V to 5.5-V V_CC operation.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

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Technical documentation

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	Type	Title	Date
*	Data sheet	SN74LVC1G57 Configurable Multiple-Function Gate datasheet (Rev. P)	29 Nov 2016
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 Jul 2021
	Selection guide	Little Logic Guide 2018 (Rev. G)	06 Jul 2018
	Selection guide	Logic Guide (Rev. AB)	12 Jun 2017
	Application note	How to Select Little Logic (Rev. A)	26 Jul 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 Dec 2015
	Application note	Understanding Schmitt Triggers	21 Sep 2011
	User guide	LOGIC Pocket Data Book (Rev. B)	16 Jan 2007
	More literature	Design Summary for WCSP Little Logic (Rev. B)	04 Nov 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	22 Jun 2004
	User guide	Signal Switch Data Book (Rev. A)	14 Nov 2003
	Application note	Use of the CMOS Unbuffered Inverter in Oscillator Circuits	06 Nov 2003
	More literature	Logic Cross-Reference (Rev. A)	07 Oct 2003
	User guide	LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)	18 Dec 2002
	Application note	Texas Instruments Little Logic Application Report	01 Nov 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 Aug 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards	13 Jun 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)	22 May 2002
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices	10 May 2002
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS	27 Mar 2002
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices	01 Dec 1997
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	01 Aug 1997
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	01 Jun 1997
	Application note	LVC Characterization Information	01 Dec 1996
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 Oct 1996
	Application note	Live Insertion	01 Oct 1996
	Design guide	Low-Voltage Logic (LVC) Designer's Guide	01 Sep 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide	01 May 1996

Design & development

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Evaluation board

5-8-LOGIC-EVM — Generic logic EVM supporting 5 through 8 pin DCK, DCT, DCU, DRL, and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.

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Simulation model

SN74LVC1G57 IBIS Model (Rev. A)

SCEM292A.ZIP (44 KB) - IBIS Model

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