Product details
Parameters
Package | Pins | Size
Features
- Available in Texas Instruments NanoFree Package
- Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 5.3 ns at 3.3 V
- Low Power Consumption, 10-μA Max ICC
- ±24-mA Output Drive at 3.3 V
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
- Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection
- Support Translation Down (5V to 3.3V and 3.3V to 1.8V)
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Description
This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A ⋅ B or Y = A + B in positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic devices
Design tools & simulation
Reference designs
Design files
-
download TIDA-010049 BOM.pdf (49KB) -
download TIDA-010049 Assembly Drawing.pdf (510KB) -
download TIDA-010049 PCB.pdf (2566KB) -
download TIDA-010049 CAD Files.zip (2441KB) -
download TIDA-010049 Gerber.zip (589KB)
Design files
Design files
Design files
Design files
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
DSBGA (YZP) | 8 | View options |
SM8 (DCT) | 8 | View options |
VSSOP (DCU) | 8 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
TI E2E™ forums with technical support from TI engineers
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