Home Logic & voltage translation Logic gates NAND gates
Home
Logic & voltage translation
Logic gates
NAND gates

SN74LVC2G132

ACTIVE

2-ch, 2-input, 1.65-V to 5.5-V NAND gates with Schmitt-Trigger inputs

Order now
Data sheet

SN74LVC2G132

ACTIVE
Data sheet Order now

Product details

Technology Family LVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 5.5 Number of channels (#) 2 Inputs per channel 2 IOL (Max) (mA) 32 IOH (Max) (mA) -32 Input type Schmitt-Trigger Output type Push-Pull Features Partial power down (Ioff), Over-voltage tolerant inputs, Ultra high speed (tpd <5ns) Data rate (Max) (Mbps) 100 Rating Catalog
Technology Family LVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 5.5 Number of channels (#) 2 Inputs per channel 2 IOL (Max) (mA) 32 IOH (Max) (mA) -32 Input type Schmitt-Trigger Output type Push-Pull Features Partial power down (Ioff), Over-voltage tolerant inputs, Ultra high speed (tpd <5ns) Data rate (Max) (Mbps) 100 Rating Catalog
DSBGA (YZP) 8 3 mm² .928 x 1.928 SSOP (DCT) 8 8 mm² 2.95 x 2.80 SSOP (DCT) 8 8 mm² 3 x 2.8 VSSOP (DCU) 8 6 mm² 2 x 3.1
  • Available in Texas Instruments NanoFree Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.3 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection
  • Support Translation Down (5V to 3.3V and 3.3V to 1.8V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in Texas Instruments NanoFree Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.3 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection
  • Support Translation Down (5V to 3.3V and 3.3V to 1.8V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A ⋅ B or Y = A + B in positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A ⋅ B or Y = A + B in positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
open-in-new Find other NAND gates
Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 28
Type Title Date
* Data sheet Dual 2-Input NAND Gate With Schmitt-Trigger Inputs datasheet (Rev. D) 24 Dec 2013
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic EVM supporting 5 through 8 pin DCK, DCT, DCU, DRL, and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
Not available on TI.com
Simulation model

SN74LVC2G132 IBIS Model (Rev. A)

SCEM411A.ZIP (44 KB) - IBIS Model
Download
Simulation model

SN74LVC2G132 Behavioral SPICE Model

SCEM617.ZIP (7 KB) - PSpice Model
Download
Reference designs

TIDA-010049 — TUV-assessed digital input reference design for IEC 61508 (SIL-2)

This 8-channel, group-isolated, digital input module reference design, focuses on applications with the need for industrial functional safety. This design has diagnostics implemented to help detect both permanent and transient random hardware faults. The concept of this input module has been (...)
document-pdfAcrobat Schematic
document-pdfAcrobat User guide
Reference designs

TIDA-01487 — Isolated CAN Flexible Data (FD) Rate Repeater Reference Design

CAN and CANopen are legacy Fieldbus protocols used in many applications in factory automation. Whenever high voltage can damage the end equipment, there is need for isolation. This isolated CAN flexible data (FD) rate repeater reference design adds electrical isolation between two CAN (...)
document-pdfAcrobat Schematic
Reference designs

TIDEP0076 — 3D Machine Vision Reference Design Based on AM572x Processor with DLP® Structured Light

The TIDEP0076 3D machine vision design describes an embedded 3D scanner based on the structured light principle. A digital camera along with a Sitara™ AM57xx processor System on Chip (SoC)  is used to capture reflected light patterns from a DLP4500-based projector. Subsquent processing (...)
document-generic Schematic
Reference designs

TIDEP0046 — Monte-Carlo Simulation on AM57x Using OpenCL for DSP Acceleration Reference Design

TI’s high performance ARM® Cortex®-A15 based AM57x processors also integrate C66x DSPs. These DSPs were designed to handle high signal and data processing tasks that are often required by industrial, automotive and financial applications. The AM57x OpenCL implementation makes it easy (...)
document-generic Schematic
Reference designs

TIDEP0047 — Power and Thermal Design Considerations Using TI's AM57x Processor Reference Design

This is a reference design based on the AM57x processor and companion TPS659037 power management integrated circuit (PMIC).  This design specifically highlights important power and thermal design considerations and techniques for systems designed with AM57x and TPS659037.  It includes (...)
document-generic Schematic
Package Pins Download
DSBGA (YZP) 8 View options
SM8 (DCT) 8 View options
VSSOP (DCU) 8 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos