These octal latches are designed specifically for low-voltage
(3.3-V) VCC operation, but with the capability to provide
a TTL interface to a 5-V system environment.
The eight latches of the 'LVT573 are transparent D-type latches.
While the latch-enable (LE) input is high, the Q outputs follow the
data (D) inputs. When LE is taken low, the Q outputs are latched at
the logic levels set up at the D inputs.
A buffered output-enable
input can be used to place the eight outputs in either a normal logic
state (high or low logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive
provide the capability to drive bus lines without need for interface
or pullup components. does not affect the
internal operations of the latches. Old data can be retained or new
data can be entered while the outputs are in the high-impedance
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down,
should be tied
to VCC through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the
The SN74LVT573 is available in TI's shrink small-outline package
(DB), which provides the same I/O pin count and functionality of
standard small-outline packages in less than half the
The SN54LVT573 is characterized for operation over the full
military temperature range of -55°C to 125°C. The
SN74LVT573 is characterized for operation from -40°C to