These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
|Part number||Order||Technology Family||VCC (Min) (V)||VCC (Max) (V)||Bits (#)||Voltage (Nom) (V)||F @ nom voltage (Max) (MHz)||ICC @ nom voltage (Max) (mA)||tpd @ nom Voltage (Max) (ns)||IOL (Max) (mA)||IOH (Max) (mA)||3-state output||Operating temperature range (C)|
||LVT||2.7||3.6||8||3.3||160||5||4.9||64||-32||No||-40 to 85|