SN75LVDS83B

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10- to 135-MHz 28-bit LVDS transmitter/serializer & FlatLink™ integrated circuit

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Product details

Parameters

Function Serializer Rating Catalog Operating temperature range (C) -10 to 70 open-in-new Find other Display SerDes

Package | Pins | Size

TSSOP (DGG) 56 113 mm² 14 x 8.1 open-in-new Find other Display SerDes

Features

  • LVDS Display Series Interfaces Directly to LCD
    Display Panels With Integrated LVDS
  • Package Options: 4.5-mm × 7-mm BGA,
    and 8.1-mm × 14-mm TSSOP
  • 1.8-V Up to 3.3-V Tolerant Data Inputs to Connect
    Directly to Low-Power, Low-Voltage Application and
    Graphic Processors
  • Transfer Rate up to 135 Mpps (Mega Pixel Per Second);
    Pixel Clock Frequency Range 10 MHz to 135 MHz
  • Suited for Display Resolutions Ranging From HVGA
    up to HD With Low EMI
  • Operates From a Single 3.3-V Supply and 170 mW (Typ.)
    at 75 MHz
  • 28 Data Channels Plus Clock in Low-Voltage TTL to 4
    Data Channels Plus Clock Out Low-Voltage Differential
  • Consumes Less Than 1 mW When Disabled
  • Selectable Rising or Falling Clock Edge Triggered
    Inputs
  • ESD: 5-kV HBM
  • Support Spread Spectrum Clocking (SSC)
  • Compatible with all OMAP™ 2x, OMAP™ 3x, and
    DaVinci™ Application Processors
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Description

The SN75LVDS83B FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS83B requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level.

The SN75LVDS83B is characterized for operation over ambient air temperatures of –10°C to 70°C.

Alternative device option: The SN75LVDS83A (SLLS980) is an alternative to the SN75LVDS83B for clock frequency range of 10MHz-100MHz only. The SN75LVDS83A is available in the TSSOP package option only.

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Technical documentation

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No results found. Please clear your search and try again. View all 5
Type Title Date
* Datasheet SN75LVDS83B FlatLink™ Transmitter datasheet (Rev. C) Jul. 29, 2014
Application notes AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (Rev. A) Aug. 03, 2018
Application notes How to Bridge HDMI/DVI to LVDS/OLDI (Rev. C) Jun. 07, 2018
Technical articles Applications of Low Voltage Differential Signaling (LVDS) in Multifunction and Industrial Printers Aug. 24, 2017
Application notes FlatLink™ Data Transmission System Using SN75LVDS83B/SN75LVDS82/SN75LVDS86A Feb. 02, 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
$2,324.44
Description

The J6Entry/RSP EVM is an evaluation platform designed to speed up development efforts and reduce time to market for applications such as Infotainment, reconfigurable Digital Cluster or Integrated Digital Cockpit.

The main CPU board integrates these key peripherals such as Ethernet or HDMI, while the (...)

Features
  • 10.1" Display with capacitive Touch
  • JAMR3 Radio Tuner Application Board
  • 2GB DDR3L
  • LP8733/LP8732 Power Solution
  • On-board eMMC, NAND, NOR
  • USB3, USB2, PCIe, Ethernet, COM8Q, CAN, MLB, MicroSD and HDMI connectors
EVALUATION BOARDS Download
$485.00
Description
The Display Application Board is an application board to be used as a display plus multi-touch touch screen daughter board used on the J6Entry, RSP and TDA2E-17 CPU EVM boards.
Features
  • 10.1" AUO Display (1280X800) with capacitive Multi-Touch
  • 24 bit Parallel interface to the CPU board EVM
EVALUATION BOARDS Download
document-generic User guide
$599.00
Description
The SN75LVDS83B transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted (...)
Features
  • Plug and play design
  • Power the EVM by USB VBUS or 5- to 5.5-V DC IN through a power jack J3
  • Access the I2C bus through headers
  • Configurable through dip Switches

Design tools & simulation

SIMULATION MODELS Download
SLLM077.ZIP (31 KB) - IBIS Model
SIMULATION TOOLS Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

Reference designs

REFERENCE DESIGNS Download
RGB to OLDI/LVDS Display Bridge Reference Design for Sitara™ Processors
TIDA-010013 — Higher resolution displays are now in larger demand than ever before. This results in a higher pixel clock which can lead to challenges such as high EMI emission and noise immunity. As a result, the video interface now transitions from a traditional RGB to LVDS video interface. As microprocessors (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
BGA MICROSTAR JUNIOR (ZQL) 56 View options
TSSOP (DGG) 56 View options

Ordering & quality

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Videos

High-speed layout guidelines for reducing EMI in LVDS SerDes designs

This video provides guidelines on how to reduce EMI in designs that use TI serializers and deserializers.

Posted: 13-Jan-2018
Duration: 08:16

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