10- to 135-MHz 28-bit LVDS transmitter/serializer & FlatLink™ integrated circuit
Product details
Parameters
Package | Pins | Size
Features
- LVDS Display Series Interfaces Directly to LCD
Display Panels With Integrated LVDS - Package Options: 4.5-mm × 7-mm BGA,
and 8.1-mm × 14-mm TSSOP - 1.8-V Up to 3.3-V Tolerant Data Inputs to Connect
Directly to Low-Power, Low-Voltage Application and
Graphic Processors - Transfer Rate up to 135 Mpps (Mega Pixel Per Second);
Pixel Clock Frequency Range 10 MHz to 135 MHz - Suited for Display Resolutions Ranging From HVGA
up to HD With Low EMI - Operates From a Single 3.3-V Supply and 170 mW (Typ.)
at 75 MHz - 28 Data Channels Plus Clock in Low-Voltage TTL to 4
Data Channels Plus Clock Out Low-Voltage Differential - Consumes Less Than 1 mW When Disabled
- Selectable Rising or Falling Clock Edge Triggered
Inputs - ESD: 5-kV HBM
- Support Spread Spectrum Clocking (SSC)
- Compatible with all OMAP™ 2x, OMAP™ 3x, and
DaVinci™ Application Processors
Description
The SN75LVDS83B FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS receiver.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN75LVDS83B requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level.
The SN75LVDS83B is characterized for operation over ambient air temperatures of 10°C to 70°C.
Alternative device option: The SN75LVDS83A (SLLS980) is an alternative to the SN75LVDS83B for clock frequency range of 10MHz-100MHz only. The SN75LVDS83A is available in the TSSOP package option only.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | SN75LVDS83B FlatLink™ Transmitter datasheet (Rev. C) | Jul. 29, 2014 |
Technical article | How to choose a power supply for an automotive camera module | Sep. 17, 2020 | |
Application note | AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (Rev. A) | Aug. 03, 2018 | |
Application note | How to Bridge HDMI/DVI to LVDS/OLDI (Rev. C) | Jun. 07, 2018 | |
Technical article | Applications of Low Voltage Differential Signaling (LVDS) in Multifunction and Industrial Printers | Aug. 24, 2017 | |
Application note | FlatLink™ Data Transmission System Using SN75LVDS83B/SN75LVDS82/SN75LVDS86A | Feb. 02, 2010 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The J6Entry/RSP EVM is an evaluation platform designed to speed up development efforts and reduce time to market for applications such as Infotainment, reconfigurable Digital Cluster or Integrated Digital Cockpit.
The main CPU board integrates these key peripherals such as Ethernet or HDMI, while the (...)
Features
- 10.1" Display with capacitive Touch
- JAMR3 Radio Tuner Application Board
- 2GB DDR3L
- LP8733/LP8732 Power Solution
- On-board eMMC, NAND, NOR
- USB3, USB2, PCIe, Ethernet, COM8Q, CAN, MLB, MicroSD and HDMI connectors
Description
Features
- 10.1" AUO Display (1280X800) with capacitive Multi-Touch
- 24 bit Parallel interface to the CPU board EVM
Description
Features
- Plug and play design
- Power the EVM by USB VBUS or 5- to 5.5-V DC IN through a power jack J3
- Access the I2C bus through headers
- Configurable through dip Switches
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Reference designs
Design files
-
download TIDA-010013 BOM.pdf (41KB) -
download TIDA-010013 Assembly Drawing.pdf (182KB) -
download TIDA-010013 PCB.pdf (1128KB) -
download TIDA-010013 CAD Files.zip (1001KB) -
download TIDA-010013 Gerber.zip (641KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
TSSOP (DGG) | 56 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
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Support & training
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