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Product details

Parameters

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Package | Pins | Size

SOIC (D) 8 19 mm² 4.9 x 3.9 VSSOP (DGK) 8 15 mm² 3 x 4.9 open-in-new Find other I2C level shifters, buffers & hubs

Features

  • Operating Power-Supply Voltage Range of 2.7 V to 5.5 V
  • Supports Bidirectional Data Transfer of I2C Bus Signals
  • SDA and SCL Lines are Buffered Which Increases Fanout
  • 1-V Precharge on all SDA and SCL Lines Prevents Corruption During Live Board Insertion and Removal From Backplane
  • SDA and SCL Input Lines are Isolated From Outputs
  • Accommodates Standard Mode and Fast Mode I2C Devices
  • Improved Noise Immunity
  • Applications Include Hot Board Insertion and Bus Extension
  • Low ICC Chip Disable of < 1 µA
  • READY Open-Drain Output
  • Supports Clock Stretching, Arbitration, and Synchronization
  • Powered-Off High-Impedance I2C Pins
  • Open-Drain I2C Pins
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

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open-in-new Find other I2C level shifters, buffers & hubs

Description

The TCA4311A is a hot-swappable I2C bus buffer that supports I/O card insertion into a live backplane without corruption of the data and clock busses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, this device provides bidirectional buffering, keeping the backplane and card capacitances isolated. During insertion, the SDA and SCL lines are pre-charged to 1 V to minimize the current required to charge the parasitic capacitance of the chip.

When the I2C bus is idle, the TCA4311A can be put into shutdown mode by setting the EN pin low. When EN is high, the TCA4311A resumes normal operation. It also includes an open drain READY output pin, which indicates that the backplane and card sides are connected together. When READY is high, the SDAIN and SCLIN are connected to SDAOUT and SCLOUT. When the two sides are disconnected, READY is low.

Both the backplane and card may be powered with supply voltages ranging from 2.7 V to 5.5 V, with no restrictions on which supply voltage is higher.

The TCA4311A has standard open-drain I/Os. The size of the pull-up resistors to the I/Os depends on the system, but each side of this buffer must have a pull-up resistor. The device is designed to work with Standard Mode and Fast Mode I2C devices in addition to SMBus devices. Standard Mode I2C devices only specify 3 mA in a generic I2C system where Standard Mode devices and multiple masters are possible. Under certain conditions, high termination currents can be used.

open-in-new Find other I2C level shifters, buffers & hubs
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TCA9511A ACTIVE 2-bit bidirectional 2.3- to 5.5-V hot swappable 400-kHz I2C/SMBus buffer The pin-to-pin device has improved performance (wider supply voltage rail, lower voltage offset, and wider temperature range).

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 7
Type Title Date
* Datasheet TCA4311A Hot Swappable 2-Wire Bus Buffers datasheet (Rev. C) Aug. 16, 2018
Application note I2C Solutions for Hot Swap Applications Jan. 31, 2020
Application note Why, When, and How to use I2C Buffers May 23, 2018
Application note Choosing the Correct I2C Device for New Designs Sep. 07, 2016
Application note Understanding the I2C Bus Jun. 30, 2015
Application note Maximum Clock Frequency of I2C Bus Using Repeaters May 15, 2015
Application note I2C Bus Pull-Up Resistor Calculation Feb. 13, 2015

Design & development

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Design tools & simulation

SIMULATION MODEL Download
SCPM046.ZIP (44 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOL Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide
DESIGN TOOL Download
I2C designer tool
I2C-DESIGNER — Use the I2C Designer tool to quickly resolve conflicts in addressing, voltage level and frequency in I2C based designs. Enter master and slave inputs to automatically generate an I2C tree or easily build a custom solution. This tool will help designers save time and comply with the I2C standard with (...)
Features
  • GUI-based web application
  • Exportable designs
  • JSON file uploader
  • Bill of materials generator

CAD/CAE symbols

Package Pins Download
SOIC (D) 8 View options
VSSOP (DGK) 8 View options

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