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Parameters

Number of channels (#) 4 FIFOs (bytes) 64 Rx FIFO trigger levels (#) 16 Tx FIFO trigger levels (#) 16 Programmable FIFO trigger levels Yes CPU interface X86 Baud rate (max) at Vcc = 1.8 V & with 16X sampling (Mbps) 1 Baud rate (max) at Vcc = 2.5 V & with 16X sampling (Mbps) 1.5 Baud rate (max) at Vcc = 3.3 V & with 16X sampling (Mbps) 2 Baud rate (max) at Vcc = 5.0 V & with 16X sampling (Mbps) 3 Operating voltage (V) 1.8, 2.5, 3.3, 5 Auto RTS/CTS Yes Rating Catalog Operating temperature range (C) 0 to 70, -40 to 85 open-in-new Find other UARTs

Package | Pins | Size

LQFP (PM) 64 100 mm² 10 x 10 open-in-new Find other UARTs

Features

  • ST16C654/654D Pin Compatible With Additional Enhancements
  • Support up to:
    • 24-MHz Crystal Input Clock (1.5 Mbps)
    • 48-MHz Oscillator Input Clock (3 Mbps) for 5-V Operation
    • 32-MHz Oscillator Input Clock (2 Mbps) for 3.3-V Operation
    • 24-MHz Input Clock (1.5 Mbps) for 2.5-V Operation
    • 16-MHz Input Clock (1 Mbps) for 1.8-V Operation
  • 64-Byte Transmit FIFO
  • 64-Byte Receive FIFO With Error Flags
  • Programmable and Selectable Transmit and Receive FIFO Trigger
    Levels for DMA and Interrupt Generation
  • Programmable Receive FIFO Trigger Levels for Software/Hardware
    Flow Control
  • Software/Hardware Flow Control
    • Programmable Xon/Xoff Characters
    • Programmable Auto-RTS and Auto-CTS
  • Optional Data Flow Resume by Xon Any Character
  • RS-485 Mode Support
  • Support 1.8-V, 2.5-V, 3.3-V, or 5-V Supply
  • Characterized for Operation From –40°C to 85°C,
    Available in Commercial and Industrial Temperature Grades
  • Software-Selectable Baud-Rate Generator
  • Prescaler Provides Additional Divide-by-4 Function
  • Programmable Sleep Mode
  • Programmable Serial Interface Characteristics
    • 5-, 6-, 7-, or 8-Bit Characters
    • Even, Odd, or No Parity Bit Generation and Detection
    • 1-, 1.5-, or 2-Stop Bit Generation
  • False Start Bit Detection
  • Complete Status Reporting Capabilities in Both Normal and Sleep Mode
  • Line Break Generation and Detection
  • Internal Test and Loopback Capabilities
  • Fully Prioritized Interrupt System Controls
  • Modem Control Functions (CTS, RTS, DSR, DTR, RI, and CD)
  • Infrared Data Association (IrDA) Capability

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Description

The ’754C is a quad universal asynchronous receiver transmitter (UART) with 64-byte FIFOs, automatic hardware and software flow control, and data rates up to 3 Mbps. It incorporates the functionality of four UARTs, each UART having its own register set and FIFOs. The four UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is Asynchronous Communications Element (ACE), and these terms are used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that four such devices are incorporated into the ’754C. The ’754C offers enhanced features. It has a transmission control register (TCR) that stores received FIFO threshold level to start or stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics.

Each UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1-, 1.5-, or 2-stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and software flow control and hardware flow control capabilities.

The ’754C is available in a 64-pin TQFP PM package. RXRDY and TXRDY functionality is not supported in the TL16C754CPM device.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 3
Type Title Date
* Datasheet TL16CP754C, TL16C754C - Quad UARTs With 64-Byte FIFO datasheet (Rev. H) Jan. 10, 2014
* Errata Short STOP Bit Errata (Rev. A) Oct. 08, 2010
More literature UART Quick Reference Card (Rev. D) Apr. 09, 2008

Design & development

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PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)

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LQFP (PM) 64 View options

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