Product details


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Package | Pins | Size

SOIC (D) 8 19 mm² 4.9 x 3.9 VSON (DRB) 8 9 mm² 3 x 3 open-in-new Find other CAN & LIN transceivers & SBCs


  • AEC-Q100 Qualified for automotive applications
    • Temperature grade 1: –40°C to 125°C TA
    • Device HBM certification level: ±8 kV
    • Device CDM certification level: ±1.5 kV
  • Compliant to LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2 A and ISO/DIS 17987–4.2 (See SLLA490)
  • Conforms to SAE J2602 recommended practice for LIN (See SLLA490)
  • Supports 24 V applications
  • LIN transmit data rate up to 20-kbps
  • Wide operating ranges
    • 4-V to 48-V Supply voltage
    • ±60-V LIN bus fault protection
  • Sleep mode: ultra-low current consumption allows wake-up event from:
    • LIN bus
    • Local wake up through EN
  • Power up and down glitch free operation
  • Protection features:
    • Under voltage protection on VSUP
    • TXD Dominant time out protection (DTO)
    • Thermal shutdown protection
    • Unpowered node or ground disconnection failsafe at system level.
  • Available in SOIC (8) and leadless VSON (8) packages with improved automated optical inspection (AOI) capability
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The TLIN2029-Q1 is a local interconnect network (LIN) physical layer transceiver with integrated wake-up and protection features, compliant to LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2 A and ISO/DIS 17987–4.2 standards. LIN is a single-wire bidirectional bus typically used for low speed in-vehicle networks using data rates up to 20 kbps. The TLIN2029-Q1 is designed to support 24-V applications with wider operating voltage and additional bus-fault protection. The LIN receiver supports data rates up to 100 kbps for faster in-line programming. The TLIN2029-Q1 converts the LIN protocol data stream on the TXD input into a LIN bus signal using a current-limited wave-shaping driver which reduces electromagnetic emissions (EME). The receiver converts the data stream to logic level signals that are sent to the microprocessor through the open-drain RXD pin. Ultra-low current consumption is possible using the sleep mode which allows wake-up via LIN bus or pin.

The integrated resistor, electrostatic discharge (ESD) and fault protection allows designers to save board space in their applications.

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Technical documentation

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Type Title Date
* Data sheet TLIN2029-Q1 Fault Protected Local Interconnect Network (LIN) Transceiver with Dominant State Timeout datasheet (Rev. E) May 20, 2020
* Errata TLIN1029-Q1 and TLIN2029-Q1 Duty Cycle Over VSUP May 22, 2020
User guide SPI to CAN FD SBC + LIN Transceiver BoosterPack User's Guide Apr. 01, 2019
Application note CAN and LIN transceiver low-power modes Feb. 25, 2019
Technical article Transients in 24V automobiles Feb. 28, 2018
Application note LIN Protocol and Physical Layer Requirements Feb. 28, 2018
Technical article Local Interconnect Network – the last mile network Jan. 18, 2018
User guide TLIN2029-Q1 EVM User's Guide Sep. 18, 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide
The SPI to CAN FD SBC + LIN BoosterPack™ plug-in module features the TCAN4550-Q1 CAN FD controller with integrated transceiver providing microcontrollers without an integrated CAN FD controller, or those needing additional channels, access to CAN FD applications through a SPI interface (...)
  • TCAN4550-Q1 CAN FD controller with integrated transceiver and SPI interface
  • TLIN2029-Q1 fault protected LIN transceiver
  • TPS7B7702-Q1 automotive dual-channel LDO
  • Common DB9 connector for supply voltage, CAN FD, and LIN bus signals
  • Follows the BoosterPack pinout standard
document-generic User guide
This EVM helps designers evaluate device performance, support fast development and analyze automotive local interconnect network (LIN) systems using TLIN2029 LIN physical layer transceiver devices.
  • Easy access to all pins of the LIN transceiver
  • Master node pullup resistance can be enabled by a series jumper
  • Pads provided for common protection and filtering components

Design tools & simulation

SLLM401.ZIP (32 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

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SOIC (D) 8 View options
SON (DRB) 8 View options

Ordering & quality

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