Product details


Number of supplies monitored 1 Threshold voltage 1 (Typ) (V) Adjustable, 1.11, 1.15, 1.67, 1.72, 2.79, 2.88, 3.06, 3.16, 4.65, 4.8 Features Undervoltage and overvoltage monitor, Watchdog disable, Watchdog timer, Window watchdog Reset threshold accuracy (%) 0.8 Output driver type/reset output Active-low, Open-drain Time delay (ms) Programmable Rating Catalog Watchdog timer WDI (sec) Programmable Operating temperature range (C) -40 to 125 open-in-new Find other Supervisor & reset ICs

Package | Pins | Size

VSON (DRC) 10 9 mm² 3 x 3 open-in-new Find other Supervisor & reset ICs


  • Input voltage range: VDD = 1.6 V to 6.5 V
  • 0.8% Voltage threshold accuracy
  • Low supply current: IDD = 10 µA (typical)
  • User-programmable watchdog timeout
  • User-programmable reset delay
  • Factory-programmed precision watchdog and reset timers
  • Open-drain outputs
  • Precision over- and undervoltage monitoring:
    • Supports common rails from 0.9 V to 5.0 V
    • ±4% and ±7% Fault windows available
    • 0.5% Hysteresis
  • Watchdog disable feature
  • Available in a small 3-mm × 3-mm, 10-Pin VSON package
  • Junction operating temperature range: –40°C to +125°C
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The TPS3850 combines a precision voltage supervisor with a programmable window watchdog timer. The TPS3850 window comparator achieves 0.8% accuracy (–40°C to +125°C) for both overvoltage (VIT+(OV)) and undervoltage (VIT–(UV)) thresholds on the SENSE pin. The TPS3850 also includes accurate hysteresis on both thresholds, making the device ideal for use with tight tolerance systems. The supervisor RESET delay can be set by factory-programmed default delay settings, or programmed by an external capacitor. The factory-programmed RESET delay features a 9.5% accuracy, high-precision delay timing.

The TPS3850 includes a programmable window watchdog timer for a wide variety of applications. The dedicated watchdog output ( WDO) enables increased resolution to help determine the nature of fault conditions. The window watchdog timeouts can be set by factory-programmed default delay settings, or programmed by an external capacitor. The watchdog can be disabled via logic pins to avoid undesired watchdog timeouts during the development process.

The TPS3850 is available in a small 3.00-mm × 3.00-mm, 10-pin VSON package.

open-in-new Find other Supervisor & reset ICs
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TPS3850-Q1 ACTIVE Automotive, window supervisor for OV & UV monitoring with window watchdog timer & programmable delay AEC-Q100 qualified version of this device
Similar functionality to the compared device.
TPS3430 ACTIVE Window watchdog timer with programmable reset delay A standalone window watchdog timer to sense both early and late faults
TPS3431 ACTIVE Standard programmable watchdog timer with enable A standalone watchdog timer with no built-in voltage monitoring feature

Technical documentation

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Type Title Date
* Data sheet TPS3850 Precision Voltage Supervisor with Programmable Window Watchdog Timer datasheet (Rev. B) Sep. 09, 2021
Application note Voltage Supervisors (Reset ICs): Frequently Asked Questions (FAQs) (Rev. A) Mar. 17, 2020
E-book Voltage Supervisor and Reset ICs: Tips, Tricks and Basics Jun. 28, 2019
Application note Comparing Voltage and Processor Monitoring Solutions Apr. 05, 2019
Application note How Comparator Topology Influences Propagation Delay Apr. 05, 2017
Technical article Exploring watchdog timer applications Feb. 02, 2017
User guide TPS3850EVM-781 Evaluation Module Oct. 24, 2016

Design & development

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Hardware development

document-generic User guide
The TPS3850EVM-781 evaluation module (EVM) is designed for a typical configuration to evaluate the operation and performance of the TPS3850 low-quiescent current (Iq), 0.8% accurate supervisor with integrated watchdog timer.
  • High threshold accuracy: 0.8%
  • User-programmable watchdog timer
  • User-programmable reset delay
  • Open-drain RESET output
  • Independent open-drain watchdog output

Design tools & simulation

SBVM648A.ZIP (9 KB) - PSpice Model
SBVM649A.ZIP (67 KB) - PSpice Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

Reference designs

High fidelity, near-field two-way audio reference design with noise reduction and echo cancellation
TIDA-01589 — Man machine interaction requires an acoustic interface for providing full duplex hands-free communication. In hands-free mode, part of the far-end or near-end audio signal from the speaker is coupled to the microphones. Furthermore, in noisy environments the microphones also capture ambient noise in (...)
document-generic Schematic

CAD/CAE symbols

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VSON (DRC) 10 View options

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