Top

Product details

Parameters

Operating temperature range (C) 0 to 70 open-in-new Find other Other interfaces

Package | Pins | Size

TQFP (PZT) 100 256 mm² 16 x 16 open-in-new Find other Other interfaces

Features

  • 3.3-V and 5-V PCI bus signaling
  • 3.3-V supply (core voltage is internally regulated to 1.8 V)
  • Serial bus data rates of 100M bits/s, 200M bits/s, and 400M bits/s
  • Physical write posting of up to three outstanding transactions
  • Serial ROM interface supports 2-wire devices
  • External cycle timer control for customized synchronization
  • PCI burst transfers and deep FIFOs to tolerate large host latency
  • Two general-purpose I/Os
  • Fabricated in advanced low-power CMOS process
  • Packaged in 100-terminal LQFP (PZT)
  • PCI_CLKRUN\ protocol

OHCI-Lynx and TI are trademarks of Texas Instruments.

open-in-new Find other Other interfaces

Description

The Texas Instruments TSB12LV26 device is a PCI-to-1394 host controller compliant with the PCI Local Bus Specification, PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, and 1394 Open Host Controller Interface Specification. The chip provides the IEEE 1394 link function and is compatible with 100M bits/s, 200M bits/s, and 400M bits/s serial bus data rates.

As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI and provides plug-and-play (PnP) compatibility. Furthermore, the TSB12LV26 device is compliant with the PCI Bus Power Management Interface Specification, per the PC 99 Design Guide requirements. TSB12LV26 device supports the D0, D2, and D3 power states.

The TSB12LV26 design provides PCI bus master bursting and is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Since PCI latency can be large, deep FIFOs are provided to buffer 1394 data.

The TSB12LV26 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The TSB12LV26 device also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus-holding buffers on the PHY/link interface.

An advanced CMOS process achieves low power consumption and allows the TSB12LV26 device to operate at PCI clock rates up to 33 MHz.

open-in-new Find other Other interfaces
Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 2
Type Title Date
* Data sheet TSB12LV26, TSB12LV26I OHCI-Lynx PCI-Based IEEE 1394 Host Controller datasheet May 24, 2006
Application note Interfacing Between the 1394a Links and TSB41BA3A (Rev. A) Oct. 04, 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOL Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
TQFP (PZT) 100 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos