4-A/6-A, 3.0-kVRMS dual-channel isolated gate driver with 5-V UVLO
Product details
Parameters
Package | Pins | Size
Features
- Supports basic and functional isolation
- CMTI greater than 100-V/ns
- 4-A peak source, 6-A peak sink output
- Switching parameters:
- 40-ns maximum propagation delay
- 5-ns maximum delay matching
- 5.5-ns maximum pulse-width distortion
- 35-µs maximum VDD power-up delay
- Up to 18-V VDD output drive supply
- 5-V and 8-V VDD UVLO Options
- Operating temp. range (TA) –40°C to 125°C
- Narrow body SOIC-16 (D) package
- Rejects input pulses shorter than 5-ns
- TTL and CMOS compatible inputs
- Safety-related certifications:
- 4242-VPK isolation per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1 (planned)
- 3000-VRMS isolation for 1 minute per UL 1577
- CQC certification per GB4943.1-2011 (planned)
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Description
The UCC21220 and UCC21220A devices are basic and functional isolated dual-channel gate drivers with 4-A peak-source and 6-A peak-sink current. They are designed to drive power MOSFETs and GaNFETs in PFC, Isolated DC/DC, and synchronous rectification applications, with fast switching performance and robust ground bounce protection through greater than 100-V/ns common-mode transient immunity (CMTI).
These devices can be configured as two low-side drivers, two high-side drivers, or half-bridge drivers. Two outputs can be paralleled to form a single driver which doubles the drive strength for heavy load conditions due to the best-in-class delay matching performance.
Protection features include: DIS pin shuts down both outputs simultaneously when it is set high; INA/B pin rejects input transient shorter than 5-ns; both inputs and outputs can withstand –2-V spikes for 200-ns, all supplies have undervoltage lockout (UVLO), and active pull down protection clamps the output below 2.1-V when unpowered or floated.
With these features, these devices enable high efficiency, high power density, and robustness in a wide variety of power applications.
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- High performance driver with input and output interface.
- Ability to test most data sheet parameters
- Ability to compare performance of various drivers with compatible pinout
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
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Reference designs
Design files
-
download PMP30446 BOM.pdf (137KB) -
download PMP30446 Assembly Drawing.pdf (347KB) -
download PMP30446 PCB.pdf (1411KB) -
download PMP30446 CAD Files.zip (1016KB) -
download PMP30446 Gerber.zip (117KB)
Design files
-
download PMP40500 BOM.pdf (35KB) -
download PMP40500 Assembly Drawing.pdf (236KB) -
download PMP40500 PCB.pdf (1760KB) -
download PMP40500 CAD Files.zip (26KB) -
download PMP40500 Gerber.zip (609KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SOIC (D) | 16 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
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