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UCC21220A

ACTIVE

3.0kVrms, 4A/6A dual-channel isolated gate driver with disable pin & 5V UVLO for MOSFETs & GaNFETs

Product details

Number of channels 2 Isolation rating Basic Withstand isolation voltage (VISO) (Vrms) 3000 Working isolation voltage (VIOWM) (Vrms) 990 Transient isolation voltage (VIOTM) (VPK) 4242 Power switch IGBT, MOSFET Peak output current (A) 6 Features Disable Output VCC/VDD (max) (V) 18 Output VCC/VDD (min) (V) 6 Input VCC (min) (V) 3 Input VCC (max) (V) 5.5 Propagation delay time (µs) 0.028 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Bus voltage (max) (V) 990 Rise time (ns) 5 Fall time (ns) 6 Undervoltage lockout (typ) (V) 5
Number of channels 2 Isolation rating Basic Withstand isolation voltage (VISO) (Vrms) 3000 Working isolation voltage (VIOWM) (Vrms) 990 Transient isolation voltage (VIOTM) (VPK) 4242 Power switch IGBT, MOSFET Peak output current (A) 6 Features Disable Output VCC/VDD (max) (V) 18 Output VCC/VDD (min) (V) 6 Input VCC (min) (V) 3 Input VCC (max) (V) 5.5 Propagation delay time (µs) 0.028 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Bus voltage (max) (V) 990 Rise time (ns) 5 Fall time (ns) 6 Undervoltage lockout (typ) (V) 5
SOIC (D) 16 59.4 mm² 9.9 x 6
  • Supports basic and functional isolation
  • CMTI greater than 100-V/ns
  • 4-A peak source, 6-A peak sink output
  • Switching parameters:
    • 40-ns maximum propagation delay
    • 5-ns maximum delay matching
    • 5.5-ns maximum pulse-width distortion
    • 35-µs maximum VDD power-up delay
  • Up to 18-V VDD output drive supply
    • 5-V and 8-V VDD UVLO Options
  • Operating temp. range (TA) –40°C to 125°C
  • Narrow body SOIC-16 (D) package
  • Rejects input pulses shorter than 5-ns
  • TTL and CMOS compatible inputs
  • Safety-related certifications:
    • 4242-VPK isolation per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1 (planned)
    • 3000-VRMS isolation for 1 minute per UL 1577
    • CQC certification per GB4943.1-2011 (planned)
  • Supports basic and functional isolation
  • CMTI greater than 100-V/ns
  • 4-A peak source, 6-A peak sink output
  • Switching parameters:
    • 40-ns maximum propagation delay
    • 5-ns maximum delay matching
    • 5.5-ns maximum pulse-width distortion
    • 35-µs maximum VDD power-up delay
  • Up to 18-V VDD output drive supply
    • 5-V and 8-V VDD UVLO Options
  • Operating temp. range (TA) –40°C to 125°C
  • Narrow body SOIC-16 (D) package
  • Rejects input pulses shorter than 5-ns
  • TTL and CMOS compatible inputs
  • Safety-related certifications:
    • 4242-VPK isolation per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1 (planned)
    • 3000-VRMS isolation for 1 minute per UL 1577
    • CQC certification per GB4943.1-2011 (planned)

The UCC21220 and UCC21220A devices are basic and functional isolated dual-channel gate drivers with 4-A peak-source and 6-A peak-sink current. They are designed to drive power MOSFETs and GaNFETs in PFC, Isolated DC/DC, and synchronous rectification applications, with fast switching performance and robust ground bounce protection through greater than 100-V/ns common-mode transient immunity (CMTI).

These devices can be configured as two low-side drivers, two high-side drivers, or half-bridge drivers. Two outputs can be paralleled to form a single driver which doubles the drive strength for heavy load conditions due to the best-in-class delay matching performance.

Protection features include: DIS pin shuts down both outputs simultaneously when it is set high; INA/B pin rejects input transient shorter than 5-ns; both inputs and outputs can withstand –2-V spikes for 200-ns, all supplies have undervoltage lockout (UVLO), and active pull down protection clamps the output below 2.1-V when unpowered or floated.

With these features, these devices enable high efficiency, high power density, and robustness in a wide variety of power applications.

The UCC21220 and UCC21220A devices are basic and functional isolated dual-channel gate drivers with 4-A peak-source and 6-A peak-sink current. They are designed to drive power MOSFETs and GaNFETs in PFC, Isolated DC/DC, and synchronous rectification applications, with fast switching performance and robust ground bounce protection through greater than 100-V/ns common-mode transient immunity (CMTI).

These devices can be configured as two low-side drivers, two high-side drivers, or half-bridge drivers. Two outputs can be paralleled to form a single driver which doubles the drive strength for heavy load conditions due to the best-in-class delay matching performance.

Protection features include: DIS pin shuts down both outputs simultaneously when it is set high; INA/B pin rejects input transient shorter than 5-ns; both inputs and outputs can withstand –2-V spikes for 200-ns, all supplies have undervoltage lockout (UVLO), and active pull down protection clamps the output below 2.1-V when unpowered or floated.

With these features, these devices enable high efficiency, high power density, and robustness in a wide variety of power applications.

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Technical documentation

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Type Title Date
* Data sheet UCC21220, UCC21220A 4-A/6-A, Dual-Channel Basic and Functional Isolated Gate Driver With High Noise Immunity datasheet (Rev. E) PDF | HTML 01 May 2019
Certificate VDE Certificate for Basic Isolation for DIN EN IEC 60747-17 (Rev. U) 07 Feb 2023
Test report Peak Efficiency at 99%, 585-W High-Voltage Buck Reference Design 24 Apr 2020
Application note External Gate Resistor Selection Guide (Rev. A) 28 Feb 2020
Application note Understanding Peak IOH and IOL Currents (Rev. A) 28 Feb 2020
Certificate UL Certification E181974 Vol 4. Sec 9 (Rev. A) 22 Jul 2019
User guide Gate Drive Voltage vs. Efficiency 25 Apr 2019
Application note How to Drive High Voltage GaN FETs with UCC21220A 06 Mar 2019
White paper Impact of an isolated gate driver (Rev. A) 20 Feb 2019
Technical article How to achieve higher system robustness in DC drives, part 3: minimum input pulse 19 Sep 2018
Application note Common Mode Transient Immunity (CMTI) for UCC2122x Isolated Gate Drivers 19 Jul 2018
White paper Demystifying high-voltage power electronics for solar inverters 06 Jun 2018
Application note Solar Inverter Layout Considerations for UCC21220 06 Jun 2018
Technical article How to achieve higher system robustness in DC drives, part 2: interlock and deadtime 30 May 2018
Technical article How to achieve higher system robustness in DC drives, part 1: negative voltage 17 Apr 2018
EVM User's guide UCC21220EVM-009 User's Guide (Rev. B) 12 Apr 2018
Technical article Why capacitive isolation: a vital building block for sensors in smart cities 16 Jan 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

UCC21220EVM-009 — UCC21220 4-A, 6-A 3.0-kVRMS Isolated Dual-Channel Gate Driver Evaluation Module

UCC21220EVM-009 is designed for evaluating UCC21220, which is a 3.0-kVRMS Isolated Dual-Channel Gate Driver with 4.0-A source and 6.0-A sink peak current capability. This EVM could be served to evaluate the driver IC against its datsheet. The EVM can also be used as Driver IC component selection (...)
User guide: PDF
Not available on TI.com
Simulation model

UCC21220AD PSpice Transient Model

SLUM649.ZIP (58 KB) - PSpice Model
Simulation model

UCC21220AD Unencrypted PSpice Transient Model

SLUM650.ZIP (3 KB) - PSpice Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

PMP30446 — Peak efficiency at 99%, 585-W high-voltage buck reference design with standard Si-MOSFETs

This reference design converts a DC-input source in the range of 450 V to 780 V into non-isolated 390 V at 1.5 A. This is an alternative solution to SiC-FET and SiC-Diode buck converter, since the actual power stage uses only standard silicon components. In order to employ 600 V rated devices, the (...)
Test report: PDF
Schematic: PDF
Reference designs

PMP40500 — 54-VDC input, 12-V 42-A output half-bridge reference design

This 12-V, 42-A output half-bridge reference design is for bus converters in wired networking campus and branch switches. The design features high efficiency and various fault protections (over-current and short-circuit). The design provides an efficiency comparison using 3 kVRMS basic and (...)
Test report: PDF
Schematic: PDF
Package Pins Download
SOIC (D) 16 View options

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