Product details

Number of channels (#) 1 Power switch MOSFET, IGBT Peak output current (A) 5 Input VCC (Min) (V) 10 Input VCC (Max) (V) 32 Features Split Output Operating temperature range (C) -40 to 140 Rise time (ns) 15 Fall time (ns) 7 Prop delay (ns) 17 Input threshold CMOS Channel input logic Single, Non-Inverting Input negative voltage (V) -5 Rating Automotive Undervoltage lockout (Typ) 8
Number of channels (#) 1 Power switch MOSFET, IGBT Peak output current (A) 5 Input VCC (Min) (V) 10 Input VCC (Max) (V) 32 Features Split Output Operating temperature range (C) -40 to 140 Rise time (ns) 15 Fall time (ns) 7 Prop delay (ns) 17 Input threshold CMOS Channel input logic Single, Non-Inverting Input negative voltage (V) -5 Rating Automotive Undervoltage lockout (Typ) 8
SOT-23 (DBV) 6 5 mm² 2.9 x 1.6
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C4B
  • Low-Cost Gate Driver (offering optimal solution
    for driving FET and IGBTs)
  • Superior Replacement to Discrete Transistor Pair
    Drive (providing easy interface with controller)
  • CMOS Compatible Input-Logic Threshold (becomes
    fixed at VDD above 18 V)
  • Split Outputs Allow Separate Turnon and Turnoff
    Tuning
  • Enable with Fixed TTL Compatible Threshold
  • High 2.5-A Source and 5-A Sink Peak-Drive Currents
    at 18-V VDD
  • Wide VDD Range From 10 V up to 35 V
  • Input Pins Capable of Withstanding up to –5-V
    DC Below Ground
  • Output Held Low When Inputs are Floating or During
    VDD UVLO
  • Fast Propagation Delays (17-ns typical)
  • Fast Rise and Fall Times
    (15-ns and 7-ns typical with 1800-pF Load)
  • Undervoltage Lockout (UVLO)
  • Used as a High-Side or Low-Side Driver (if designed
    with proper bias and signal isolation)
  • Low-Cost Space-Saving 6-Pin DBV (SOT-23) Package
  • Operating Temperature Range of –40°C to 140°C
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C4B
  • Low-Cost Gate Driver (offering optimal solution
    for driving FET and IGBTs)
  • Superior Replacement to Discrete Transistor Pair
    Drive (providing easy interface with controller)
  • CMOS Compatible Input-Logic Threshold (becomes
    fixed at VDD above 18 V)
  • Split Outputs Allow Separate Turnon and Turnoff
    Tuning
  • Enable with Fixed TTL Compatible Threshold
  • High 2.5-A Source and 5-A Sink Peak-Drive Currents
    at 18-V VDD
  • Wide VDD Range From 10 V up to 35 V
  • Input Pins Capable of Withstanding up to –5-V
    DC Below Ground
  • Output Held Low When Inputs are Floating or During
    VDD UVLO
  • Fast Propagation Delays (17-ns typical)
  • Fast Rise and Fall Times
    (15-ns and 7-ns typical with 1800-pF Load)
  • Undervoltage Lockout (UVLO)
  • Used as a High-Side or Low-Side Driver (if designed
    with proper bias and signal isolation)
  • Low-Cost Space-Saving 6-Pin DBV (SOT-23) Package
  • Operating Temperature Range of –40°C to 140°C

The UCC27532-Q1 device is a single-channel high-speed gate driver capable of effectively driving MOSFET and IGBT power switches by up to 2.5-A source and 5-A sink (asymmetrical drive) peak current. Strong sink capability in asymmetrical drive boosts immunity against parasitic Miller turnon effect. The UCC27532-Q1 device also features a split-output configuration where the gate-drive current is sourced through the OUTH pin and sunk through the OUTL pin. This pin arrangement allows the user to apply independent turnon and turnoff resistors to the OUTH and OUTL pins respectively and easily control the switching slew rates.

The driver has rail-to-rail drive capability and an extremely-small propagation delay of 17 ns (typically).

The UCC27532-Q1 device has a CMOS-input threshold-centered 55% rise and 45% fall in regards of VDD at VDD below or equal 18 V. When VDD is above 18 V, the input threshold remains fixed at the maximum level.

The driver has an EN pin with a fixed TTL-compatible threshold. EN is internally pulled up; pulling EN low disables driver, while leaving it open provides normal operation. The EN pin can be used as an additional input with the same performance as the IN pin.

Leaving the input pin of driver open holds the output low. The logic behavior of the driver is shown in the Timing Diagram, Input/Output Logic Truth Table, and Typical Application Diagrams.

Internal circuitry on the VDD pin provides an undervoltage-lockout function that holds the output low until the VDD supply voltage is within operating range.

The UCC27532-Q1 driver is offered in a 6-pin standard SOT-23 (DBV) package. The device operates over a wide temperature range of –40°C to 140°C.

The UCC27532-Q1 device is a single-channel high-speed gate driver capable of effectively driving MOSFET and IGBT power switches by up to 2.5-A source and 5-A sink (asymmetrical drive) peak current. Strong sink capability in asymmetrical drive boosts immunity against parasitic Miller turnon effect. The UCC27532-Q1 device also features a split-output configuration where the gate-drive current is sourced through the OUTH pin and sunk through the OUTL pin. This pin arrangement allows the user to apply independent turnon and turnoff resistors to the OUTH and OUTL pins respectively and easily control the switching slew rates.

The driver has rail-to-rail drive capability and an extremely-small propagation delay of 17 ns (typically).

The UCC27532-Q1 device has a CMOS-input threshold-centered 55% rise and 45% fall in regards of VDD at VDD below or equal 18 V. When VDD is above 18 V, the input threshold remains fixed at the maximum level.

The driver has an EN pin with a fixed TTL-compatible threshold. EN is internally pulled up; pulling EN low disables driver, while leaving it open provides normal operation. The EN pin can be used as an additional input with the same performance as the IN pin.

Leaving the input pin of driver open holds the output low. The logic behavior of the driver is shown in the Timing Diagram, Input/Output Logic Truth Table, and Typical Application Diagrams.

Internal circuitry on the VDD pin provides an undervoltage-lockout function that holds the output low until the VDD supply voltage is within operating range.

The UCC27532-Q1 driver is offered in a 6-pin standard SOT-23 (DBV) package. The device operates over a wide temperature range of –40°C to 140°C.

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Evaluation board

UCC27532EVM-538 — Gate Driver daughter card with isolation based on UCC27532

The UCC27532EVM-538 is a fully isolated gate driver daughter card that provides a test platform for a quick and easy startup of the UCC27532DBV driver device. The EVM delivers a 20 V to -5 V output differential gate drive which can be used to drive SiC power MOSFETs and Si IGBTs with a negative (...)
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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