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ADC3549

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500-MSPS-ADC, 14 Bit, 1 Kanal, mit LVDS-Schnittstelle und bis zu 32768x Dezimation

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Datenblatt

document-pdfAcrobat ADC354x Single Channel 14-bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC) datasheet (Rev. C) (Englisch) PDF | HTML

ADC3549

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Sample rate (max) (Msps)

500

Resolution (Bits)

14

Number of input channels

1

Interface type

DDR LVDS

Analog input BW (MHz)

1400

Features

Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low latency, Low power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

413.1

Architecture

Pipeline

SNR (dB)

74

ENOB (Bits)

12

SFDR (dB)

83

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

Sample rate (max) (Msps)

500

Resolution (Bits)

14

Number of input channels

1

Interface type

DDR LVDS

Analog input BW (MHz)

1400

Features

Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low latency, Low power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

413.1

Architecture

Pipeline

SNR (dB)

74

ENOB (Bits)

12

SFDR (dB)

83

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

VQFNP (RTD)

64

81 mm² 9 x 9

14-bit, single channel 250 and 500MSPS ADC
Noise spectral density: -158.5dBFS/Hz
Thermal Noise: 74.5dBFS
Single core (non-interleaved) ADC architecture
Power consumption:
- 435mW (500MSPS)
- 369mW (250MSPS)
Aperture jitter: 75fs
Buffered analog inputs
- Programmable 100 and 200Ω termination
Input fullscale: 2Vpp
Full power input bandwidth (-3dB): 1.4GHz
Spectral performance (fIN = 70MHz, -1dBFS):
- SNR: 73.8dBFS
- SFDR HD2,3: 82dBc
- SFDR worst spur: 94dBFS
Digital down-converters (DDCs)
- Up to four independent DDC
- Complex and real decimation
- Decimation: 2x, 4x to 32768x decimation
- 48-bit NCO phase coherent frequency hopping
DDR/Serial LVDS interface
- 16-bit Parallel SDR, DDR LVDS for DDC bypass
- Serial LVDS for decimation
- 32-bit output option for high decimation

14-bit, single channel 250 and 500MSPS ADC
Noise spectral density: -158.5dBFS/Hz
Thermal Noise: 74.5dBFS
Single core (non-interleaved) ADC architecture
Power consumption:
- 435mW (500MSPS)
- 369mW (250MSPS)
Aperture jitter: 75fs
Buffered analog inputs
- Programmable 100 and 200Ω termination
Input fullscale: 2Vpp
Full power input bandwidth (-3dB): 1.4GHz
Spectral performance (fIN = 70MHz, -1dBFS):
- SNR: 73.8dBFS
- SFDR HD2,3: 82dBc
- SFDR worst spur: 94dBFS
Digital down-converters (DDCs)
- Up to four independent DDC
- Complex and real decimation
- Decimation: 2x, 4x to 32768x decimation
- 48-bit NCO phase coherent frequency hopping
DDR/Serial LVDS interface
- 16-bit Parallel SDR, DDR LVDS for DDC bypass
- Serial LVDS for decimation
- 32-bit output option for high decimation

The ADC3548 and ADC3549 (ADC354x) is a 14-bit, 250 and 500MSPS, single channel analog to digital converter (ADC). The device is designed for high signal-to-noise ratio (SNR) and delivers a noise spectral density as low as -158.5dBFS/Hz.

The power efficient ADC architecture consumes 435mW at 500MSPS and provides power scaling with lower sampling rates (369mW at 250MSPS).

The ADC354x includes a quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.

The ADC354x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 14-bit wide parallel SDR or DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation rates, the output resolution can be increased to 32-bit.

The ADC3548 and ADC3549 (ADC354x) is a 14-bit, 250 and 500MSPS, single channel analog to digital converter (ADC). The device is designed for high signal-to-noise ratio (SNR) and delivers a noise spectral density as low as -158.5dBFS/Hz.

The power efficient ADC architecture consumes 435mW at 500MSPS and provides power scaling with lower sampling rates (369mW at 250MSPS).

The ADC354x includes a quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.

The ADC354x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 14-bit wide parallel SDR or DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation rates, the output resolution can be increased to 32-bit.

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	Typ	Titel		Datum
*	Data sheet	ADC354x Single Channel 14-bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC) datasheet (Rev. C)	PDF \| HTML	09 Jul 2025
	Analog Design Journal	Sampling around Nyquist holes in high-speed converters	PDF \| HTML	16 Mai 2025
	Application note	Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends	PDF \| HTML	28 Mär 2025
	Application note	Evaluating High-Speed, RF ADC Converter Front-end Architectures	PDF \| HTML	26 Mär 2025
	Application note	Improving MSPS ADC’s SFDR While Relaxing AAF Requirements and Using Integrated DDC Features	PDF \| HTML	18 Feb 2025

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ADC3549

500-MSPS-ADC, 14 Bit, 1 Kanal, mit LVDS-Schnittstelle und bis zu 32768x Dezimation

ADC3549

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Technische Dokumentation

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ADC3669EVM — ADC3669 evaluation module (DC coupled)

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