CD4044B

AKTIV

CMOS-Quad-NAND-R/S-Latch mit 3-State-Ausgängen

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Datenblatt

document-pdfAcrobat CD4043B, CD4044B Types datasheet (Rev. D) (Englisch)

CD4044B

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Function

RS latch

Number of channels

4

Technology family

CD4000

Supply voltage (min) (V)

3

Supply voltage (max) (V)

18

Input type

Standard CMOS

Output type

3-State

Data rate (max) (Mbps)

16

IOL (max) (mA)

2.4

IOH (max) (mA)

-2.4

Features

High speed (tpd 10-50ns), Partial power down (Ioff), Standard speed (tpd > 50ns)

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Function

RS latch

Number of channels

4

Technology family

CD4000

Supply voltage (min) (V)

3

Supply voltage (max) (V)

18

Input type

Standard CMOS

Output type

3-State

Data rate (max) (Mbps)

16

IOL (max) (mA)

2.4

IOH (max) (mA)

-2.4

Features

High speed (tpd 10-50ns), Partial power down (Ioff), Standard speed (tpd > 50ns)

Operating temperature range (°C)

-55 to 125

Rating

Catalog

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

SOIC (DW)

16

106.09 mm² 10.3 x 10.3

SOP (NS)

16

79.56 mm² 10.2 x 7.8

TSSOP (PW)

16

32 mm² 5 x 6.4

3-state outputs with common output ENABLE
Separate SET and RESET inputs for each latch
NOR and NAND configurations
5-V, 10-V, and 15-V parametric ratings
Standardized symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
- 1 V at V_DD = 5 V
- 2 V at V_DD = 10 V
- 2.5 V at V_DD = 15 V
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
Applications
- Holding register in multi-register system
- Four bits of independent storage with output ENABLE
- Strobed register
- General digital logic
- CD4043B for positive logic systems
- CD4044B for negative logic systems

Data sheet acquired from Harris Semiconductor

3-state outputs with common output ENABLE
Separate SET and RESET inputs for each latch
NOR and NAND configurations
5-V, 10-V, and 15-V parametric ratings
Standardized symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
- 1 V at V_DD = 5 V
- 2 V at V_DD = 10 V
- 2.5 V at V_DD = 15 V
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
Applications
- Holding register in multi-register system
- Four bits of independent storage with output ENABLE
- Strobed register
- General digital logic
- CD4043B for positive logic systems
- CD4044B for negative logic systems

Data sheet acquired from Harris Semiconductor

CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.

The CD4043B and CD4044B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (D, DR, DT, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.

The CD4043B and CD4044B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (D, DR, DT, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

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Alle anzeigen 8

	Typ	Titel		Datum
*	Data sheet	CD4043B, CD4044B Types datasheet (Rev. D)		13 Okt 2003
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15 Dez 2022
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	User guide	Signal Switch Data Book (Rev. A)		14 Nov 2003
	Application note	Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics		03 Dez 2001

Design und Entwicklung

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Evaluierungsplatine

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Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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Gehäuse	Pins	Herunterladen
PDIP (N)	16	Optionen anzeigen
SOIC (D)	16	Optionen anzeigen
SOIC (DW)	16	Optionen anzeigen
SOP (NS)	16	Optionen anzeigen
TSSOP (PW)	16	Optionen anzeigen

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CD4044B

CMOS-Quad-NAND-R/S-Latch mit 3-State-Ausgängen

CD4044B

Produktdetails

Technische Dokumentation

Design und Entwicklung

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

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