CDCLVP1212

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Jitterarmer 1:12-Universal-auf-LVPECL-Puffer mit zwei auswählbaren Eingängen

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Datenblatt

document-pdfAcrobat CDCLVP1212 LVPECL Output, High-Performance Clock Buffer datasheet (Rev. E) (Englisch) PDF | HTML

CDCLVP1212

AKTIV

Datenblatt

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Produktdetails

Number of outputs

12

Additive RMS jitter (typ) (fs)

57

Core supply voltage (V)

2.5, 3.3

Output supply voltage (V)

2.5, 3.3

Output skew (ps)

25

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVPECL

Input type

LVCMOS, LVDS, LVPECL

Number of outputs

12

Additive RMS jitter (typ) (fs)

57

Core supply voltage (V)

2.5, 3.3

Output supply voltage (V)

2.5, 3.3

Output skew (ps)

25

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVPECL

Input type

LVCMOS, LVDS, LVPECL

VQFN (RHA)

40

36 mm² (6 mm × 6 mm)

2:12 Differential Buffer
Selectable Clock Inputs Through Control Terminal
Universal Inputs Accept LVPECL, LVDS, and
LVCMOS/LVTTL
12 LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 88 mA
Very Low Additive Jitter: <100 fs, rms in 10-kHz to
20-MHz Offset Range:
- 57 fs, rms (typ) @ 122.88 MHz
- 48 fs, rms (typ) @ 156.25 MHz
- 30 fs, rms (typ) @ 312.5 MHz
2.375-V to 3.6-V Device Power Supply
Maximum Propagation Delay: 550 ps
Maximum Output Skew: 25 ps
LVPECL Reference Voltage, V_{AC_REF}, Available
for Capacitive-Coupled Inputs
Industrial Temperature Range: –40°C to 85°C
ESD Protection Exceeds 2 kV (HBM)
Supports 105°C PCB Temperature (Measured
with a Thermal Pad)
Available in 6-mm × 6-mm QFN-40 (RHA) Package

2:12 Differential Buffer
Selectable Clock Inputs Through Control Terminal
Universal Inputs Accept LVPECL, LVDS, and
LVCMOS/LVTTL
12 LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 88 mA
Very Low Additive Jitter: <100 fs, rms in 10-kHz to
20-MHz Offset Range:
- 57 fs, rms (typ) @ 122.88 MHz
- 48 fs, rms (typ) @ 156.25 MHz
- 30 fs, rms (typ) @ 312.5 MHz
2.375-V to 3.6-V Device Power Supply
Maximum Propagation Delay: 550 ps
Maximum Output Skew: 25 ps
LVPECL Reference Voltage, V_{AC_REF}, Available
for Capacitive-Coupled Inputs
Industrial Temperature Range: –40°C to 85°C
ESD Protection Exceeds 2 kV (HBM)
Supports 105°C PCB Temperature (Measured
with a Thermal Pad)
Available in 6-mm × 6-mm QFN-40 (RHA) Package

The CDCLVP1212 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1212 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 25 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1212 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. The CDCLVP1212 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1212 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (V_{AC_REF}) should be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1212 is packaged in a small 40-terminal, 6-mm × 6-mm QFN package and is characterized for operation from –40°C to 85°C.

The CDCLVP1212 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1212 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 25 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1212 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. The CDCLVP1212 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1212 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (V_{AC_REF}) should be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1212 is packaged in a small 40-terminal, 6-mm × 6-mm QFN package and is characterized for operation from –40°C to 85°C.

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Top-Dokumentation	Typ	Titel	Format-Optionen	Neueste englische Version herunterladen	Datum
*	Datenblatt	CDCLVP1212 LVPECL Output, High-Performance Clock Buffer datasheet (Rev. E)	PDF \| HTML		02.12.2015
	Anwendungshinweis	Clocking Design Guidelines: Unused Pins			19.11.2015

CDCLVPxxxx IBIS Model (Rev. B)

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CDCLVP1212

Jitterarmer 1:12-Universal-auf-LVPECL-Puffer mit zwei auswählbaren Eingängen

CDCLVP1212

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