CDCLVP2104

Name: CDCLVP2104
Brand: TI
SKU: CDCLVP2104
Price: 5.313 USD

AKTIV

Jitterarmer Dual-1:4-Universal-zu-LVPECL-Puffer

Jetzt bestellen

Datenblatt

document-pdfAcrobat CDCLVP2104 Eight-LVPECL Output, High-Performance Clock Buffer datasheet (Rev. B) (Englisch) PDF | HTML

CDCLVP2104

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Number of outputs

8

Additive RMS jitter (typ) (fs)

89

Core supply voltage (V)

2.5, 3.3

Output supply voltage (V)

2.5, 3.3

Output skew (ps)

15

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVPECL

Input type

LVCMOS, LVDS, LVPECL

Number of outputs

8

Additive RMS jitter (typ) (fs)

89

Core supply voltage (V)

2.5, 3.3

Output supply voltage (V)

2.5, 3.3

Output skew (ps)

15

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVPECL

Input type

LVCMOS, LVDS, LVPECL

VQFN (RHD)

28

25 mm² 5 x 5

Dual 1:4 Differential Buffer
Two Clock Inputs
Universal Inputs Can Accept LVPECL,
LVDS, LVCMOS/LVTTL
Eight LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 78 mA
Very Low Additive Jitter: <100 fs,
RMS in 10-kHz to 20-MHz Offset Range
2.375-V to 3.6-V Device Power Supply
Maximum Propagation Delay: 450 ps
Maximum 15 ps Within Bank Output Skew
LVPECL Reference Voltage, V_{AC_REF},
Available for Capacitive-Coupled Inputs
Industrial Temperature Range: –40°C to +85°C
Supports 105°C PCB Temperature (Measured with a Thermal Pad)
Available in 5-mm × 5-mm, 28-Pin VQFN (RHD) Package
ESD Protection Exceeds 2000 V (HBM)

Dual 1:4 Differential Buffer
Two Clock Inputs
Universal Inputs Can Accept LVPECL,
LVDS, LVCMOS/LVTTL
Eight LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 78 mA
Very Low Additive Jitter: <100 fs,
RMS in 10-kHz to 20-MHz Offset Range
2.375-V to 3.6-V Device Power Supply
Maximum Propagation Delay: 450 ps
Maximum 15 ps Within Bank Output Skew
LVPECL Reference Voltage, V_{AC_REF},
Available for Capacitive-Coupled Inputs
Industrial Temperature Range: –40°C to +85°C
Supports 105°C PCB Temperature (Measured with a Thermal Pad)
Available in 5-mm × 5-mm, 28-Pin VQFN (RHD) Package
ESD Protection Exceeds 2000 V (HBM)

The CDCLVP2104 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP2104 clock buffer distributes two clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2104 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (V_{AC_REF}) must be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2104 is characterized for operation from &3150;40°C to +85°C and is available in a 5-mm × 5-mm, QFN-28 package.

The CDCLVP2104 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP2104 clock buffer distributes two clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2104 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (V_{AC_REF}) must be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2104 is characterized for operation from &3150;40°C to +85°C and is available in a 5-mm × 5-mm, QFN-28 package.

filter

Andere Taktpuffer suchen

Herunterladen Video mit Transkript ansehen Video

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Evaluierungsplatine

CDCLVP2104EVM — CDCLVP2104-Evaluierungsmodul

The CDCLVP2104 is a high-performance, low additive phase noise clock buffer. It has two universal input buffers that support either single-ended or differential clock inputs. Each input feeds a bank of four LVPECL outputs. The device also features on-chip bias generators that can provide the (...)

Benutzerhandbuch: PDF

Nicht verfügbar auf TI.com

Simulationsmodell

CDCLVPxxxx IBIS Model (Rev. B)

SLLM056B.ZIP (40 KB) - IBIS Model

Herunterladen

Designtool

CLOCK-TREE-ARCHITECT — Programmiersoftware Clock Tree Architect

Der Taktbaum-Architekt ist ein Taktbaum-Synthesetool, das Ihren Designprozess optimiert, indem es Taktbaumlösungen auf der Grundlage Ihrer Systemanforderungen erzeugt. Das Tool zieht Daten aus einer umfangreichen Datenbank von Taktgeberprodukten, um eine Multi-Chip-Taktlösung auf Systemebene zu (...)

Jetzt entwickeln

Designtool

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Unterstützte Produkte und Hardware

Download-Optionen

Simulationstool

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

PSpice® für TI ist eine Design- und Simulationsumgebung, welche Sie dabei unterstützt, die Funktionalität analoger Schaltungen zu evaluieren. Diese Design- und Simulationssuite mit vollem Funktionsumfang verwendet eine analoge Analyse-Engine von Cadence®. PSpice für TI ist kostenlos erhältlich und (...)

Anfordern

Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
VQFN (RHD)	28	Ultra Librarian

Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

Top-Dokumentation	Typ	Titel	Format-Optionen	Datum
*	Data sheet	CDCLVP2104 Eight-LVPECL Output, High-Performance Clock Buffer datasheet (Rev. B)	PDF \| HTML	25 Okt 2013
	User guide	CDCLVP2104 User's Guide		21 Okt 2009

CDCLVP2104

Jitterarmer Dual-1:4-Universal-zu-LVPECL-Puffer

CDCLVP2104

Produktdetails

Ähnliche Produkte, die für Sie interessant sein könnten

Ähnliche Funktionalität wie verglichener Baustein

Technische Dokumentation

Design und Entwicklung

CDCLVP2104EVM — CDCLVP2104-Evaluierungsmodul

CDCLVPxxxx IBIS Model (Rev. B)

CLOCK-TREE-ARCHITECT — Programmiersoftware Clock Tree Architect

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

Unterstützte Produkte und Hardware

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

Bestellen & Qualität

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Videoreihe

Videos

Download-Möglichkeiten

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

Taktpuffer

Taktgeneratoren

Takt-Jitter-Cleaner

Oszillatoren

HF-PLLs und Synthesizer

Hardware-Entwicklung

Dokumentation

Versionsinformationen

Neuheiten