The DRV8304 device is
an integrated gate driver for 3-phase brushless DC (BLDC) motors applications for 12-V and 24-V DC
rails. These applications include field-oriented control (FOC), sinusoidal current control, and
trapezoidal current control of BLDC motors. The device integrates three current-sense amplifiers
(CSA) for sensing the phase currents of BLDC motors for optimum FOC and current-control system
implementation. An AUTOCAL feature automatically calibrates the CSA offset error for accurate
current sensing.
The device is based on smart gate-drive (SGD) architecture to eliminate the need of any
external gate components (resistors and Zener diodes) while fully protecting the external FETs. The
SGD architecture optimizes dead time to avoid any shoot-through conditions, provides flexibility in
decreasing electromagnetic interference (EMI) by gate slew-rate control, and protects against any
gate-short conditions through VGS hand-shaking and dead time insertion.
Strong pulldown current also prevents any dv/dt gate turnon.
Various PWM control modes (1x, 3x, 6x, and independent) are supported for simple
interfacing to control circuits that can be powered by the 30-mA, 3.3-V internal regulator. These
modes decrease the number of output peripherals of the controller for the specific motor-control
requirements and provide flexibility of control. The device also has a 1x mode for sensored
trapezoidal control of the BLDC motor by using the internal block-commutation table. The device can
also be configured to drive multiple loads, such as solenoids, in independent mode.
The DRV8304 device is
an integrated gate driver for 3-phase brushless DC (BLDC) motors applications for 12-V and 24-V DC
rails. These applications include field-oriented control (FOC), sinusoidal current control, and
trapezoidal current control of BLDC motors. The device integrates three current-sense amplifiers
(CSA) for sensing the phase currents of BLDC motors for optimum FOC and current-control system
implementation. An AUTOCAL feature automatically calibrates the CSA offset error for accurate
current sensing.
The device is based on smart gate-drive (SGD) architecture to eliminate the need of any
external gate components (resistors and Zener diodes) while fully protecting the external FETs. The
SGD architecture optimizes dead time to avoid any shoot-through conditions, provides flexibility in
decreasing electromagnetic interference (EMI) by gate slew-rate control, and protects against any
gate-short conditions through VGS hand-shaking and dead time insertion.
Strong pulldown current also prevents any dv/dt gate turnon.
Various PWM control modes (1x, 3x, 6x, and independent) are supported for simple
interfacing to control circuits that can be powered by the 30-mA, 3.3-V internal regulator. These
modes decrease the number of output peripherals of the controller for the specific motor-control
requirements and provide flexibility of control. The device also has a 1x mode for sensored
trapezoidal control of the BLDC motor by using the internal block-commutation table. The device can
also be configured to drive multiple loads, such as solenoids, in independent mode.