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Serializer/Deserializer für FPD-Link

DS90CF564

AKTIV

Color Flat Panel Display (FPD) Link, LVDS, 18 Bit – 65 MHz

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Datenblatt

DS90CF564

AKTIV
Datenblatt Jetzt bestellen

Produktdetails

Applications In-vehicle Infotainment (IVI) Input compatibility FPD-Link LVDS Function Deserializer Output compatibility LVCMOS Color depth (bpp) 18 Features Low-EMI Point-to-Point Communication EMI reduction LVDS Rating Catalog Operating temperature range (°C) -10 to 70
Applications In-vehicle Infotainment (IVI) Input compatibility FPD-Link LVDS Function Deserializer Output compatibility LVCMOS Color depth (bpp) 18 Features Low-EMI Point-to-Point Communication EMI reduction LVDS Rating Catalog Operating temperature range (°C) -10 to 70
TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm)
  • 20 to 65 MHz Shift Clk Support
  • Up to 171 Mbytes/s Bandwidth
  • Cable Size is Reduced to Save Cost
  • 290 mV Swing LVDS Devices for Low EMI
  • Low Power CMOS Design (< 550 mW typ)
  • Power-down Mode Saves Power (< 0.25 mW)
  • PLL Requires No External Components
  • Low Profile 48-Lead TSSOP Package
  • Falling Edge Data Strobe
  • Compatible with TIA/EIA-644 LVDS Standard
  • Single Pixel Per Clock XGA (1024 x 768)
  • Supports VGA, SVGA, XGA and Higher
  • 1.3 Gbps Throughput

All trademarks are the property of their respective owners.

  • 20 to 65 MHz Shift Clk Support
  • Up to 171 Mbytes/s Bandwidth
  • Cable Size is Reduced to Save Cost
  • 290 mV Swing LVDS Devices for Low EMI
  • Low Power CMOS Design (< 550 mW typ)
  • Power-down Mode Saves Power (< 0.25 mW)
  • PLL Requires No External Components
  • Low Profile 48-Lead TSSOP Package
  • Falling Edge Data Strobe
  • Compatible with TIA/EIA-644 LVDS Standard
  • Single Pixel Per Clock XGA (1024 x 768)
  • Supports VGA, SVGA, XGA and Higher
  • 1.3 Gbps Throughput

All trademarks are the property of their respective owners.

The DS90CF563 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CF564 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 171 Mbytes per second. These devices are offered with falling edge data strobes for convenient interface with a variety of graphics and LCD panel controllers.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

The DS90CF563 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CF564 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 171 Mbytes per second. These devices are offered with falling edge data strobes for convenient interface with a variety of graphics and LCD panel controllers.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt DS90CF563/DS90CF564 LVDS 18-Bit Color Flat Panel Display(FPD) Link - 65 MHz datasheet (Rev. E) 17.04.2013
Anwendungshinweis High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 09.11.2018
Anwendungshinweis How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) 29.06.2018
Anwendungshinweis AN-1032 An Introduction to FPD-Link (Rev. C) 08.08.2017
Anwendungshinweis TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 15.05.2004
Anwendungshinweis AN-1056 STN Application Using FPD-Link 14.05.2004
Anwendungshinweis AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines 14.05.2004

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TSSOP (DGG) 48 Ultra Librarian
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