DS90CR217

AKTIV

21-Bit Channel-Link-LVDS-Sender, +3,3V Rising Edge Data Strobe – 85 MHz

Produktdetails

Protocols Catalog Device type Transmitter Rating Catalog Operating temperature range (°C) -10 to 70
Protocols Catalog Device type Transmitter Rating Catalog Operating temperature range (°C) -10 to 70
TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm)
  • 20 to 85 MHz Shift Clock Support
  • 50% Duty Cycle on Receiver Output Clock
  • Best-in-Class Set & Hold Times on TxINPUTs
  • Low Power Consumption
  • ±1V Common-Mode Range (Around +1.2V)
  • Narrow Bus Reduces Cable Size and Cost
  • Up to 1.785 Gbps Throughput
  • Up to 223 Mbytes/sec Bandwidth
  • 345 mV (typ) Swing LVDS Devices for Low EMI
  • PLL Requires No External Components
  • Rising Edge Data Strobe
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 48-Lead TSSOP Package

All trademarks are the property of their respective owners.

  • 20 to 85 MHz Shift Clock Support
  • 50% Duty Cycle on Receiver Output Clock
  • Best-in-Class Set & Hold Times on TxINPUTs
  • Low Power Consumption
  • ±1V Common-Mode Range (Around +1.2V)
  • Narrow Bus Reduces Cable Size and Cost
  • Up to 1.785 Gbps Throughput
  • Up to 223 Mbytes/sec Bandwidth
  • 345 mV (typ) Swing LVDS Devices for Low EMI
  • PLL Requires No External Components
  • Rising Edge Data Strobe
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 48-Lead TSSOP Package

All trademarks are the property of their respective owners.

The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 21 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 1.785 Gbit/s (223 Mbytes/sec).

The narrow bus and LVDS signalling of the DS90CR217 is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 21 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 1.785 Gbit/s (223 Mbytes/sec).

The narrow bus and LVDS signalling of the DS90CR217 is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt DS90CR217 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz datasheet (Rev. A) 19.02.2013
Anwendungshinweis High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 09.11.2018
Anwendungshinweis Receiver Skew Margin for Channel Link I and FPD Link I Devices PDF | HTML 13.01.2016
Anwendungshinweis Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des (Rev. A) 26.04.2013
Designleitfaden Channel Link I Design Guide 29.03.2007
Anwendungshinweis Multi-Drop Channel-Link Operation 04.10.2004
Anwendungshinweis CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications 05.10.1998

Design und Entwicklung

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Simulationsmodell

DS90CR217 IBIS Model

SNLM056.ZIP (7 KB) - IBIS-Modell
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