DS90CR218A

AKTIV

21-Bit Channel-Link-LVDS-Empfänger, +3,3V Rising Edge Data Strobe – 85 MHz

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Datenblatt

document-pdfAcrobat DS90CR218A 3.3VRising Edge Data Strobe LVDS 21Bit Chan Link 12MHz to 85MHz datasheet (Rev. D) (Englisch)

DS90CR218A

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Protocols

Catalog

Rating

Catalog

Operating temperature range (°C)

-10 to 70

Protocols

Catalog

Rating

Catalog

Operating temperature range (°C)

-10 to 70

TSSOP (DGG)

48

101.25 mm² (12.5 mm × 8.1 mm)

12 to 85 MHz Shift Clock Support
50% Duty Cycle on Receiver Output Clock
Low Power Consumption
±1V Common-mode Range (Around +1.2V)
Narrow Bus Reduces Cable Size and Cost
Up to 1.785 Gbps Throughput
Up to 223 Mbytes/sec Bandwidth
345 mV (typ) Swing LVDS Devices for Low EMI
PLL Requires No External Components
Rising Edge Data Strobe
Compatible with TIA/EIA-644 LVDS Standard
Low Profile 48-Lead TSSOP Package

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12 to 85 MHz Shift Clock Support
50% Duty Cycle on Receiver Output Clock
Low Power Consumption
±1V Common-mode Range (Around +1.2V)
Narrow Bus Reduces Cable Size and Cost
Up to 1.785 Gbps Throughput
Up to 223 Mbytes/sec Bandwidth
345 mV (typ) Swing LVDS Devices for Low EMI
PLL Requires No External Components
Rising Edge Data Strobe
Compatible with TIA/EIA-644 LVDS Standard
Low Profile 48-Lead TSSOP Package

All trademarks are the property of their respective owners.

The DS90CR218A receiver deserializes three input LVDS data streams into 21 bits of CMOS/TTL output data. When operating at the maximum input clock rate of 85 Mhz, the LVDS data is received at 595 Mbps per data channel for a total data throughput of 1.785 Gbit/sec (233 Mbytes/sec).

The narrow bus and LVDS signalling of the DS90CR218A is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

The DS90CR218A receiver deserializes three input LVDS data streams into 21 bits of CMOS/TTL output data. When operating at the maximum input clock rate of 85 Mhz, the LVDS data is received at 595 Mbps per data channel for a total data throughput of 1.785 Gbit/sec (233 Mbytes/sec).

The narrow bus and LVDS signalling of the DS90CR218A is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

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Technische Dokumentation

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Top-Dokumentation	Typ	Titel	Format-Optionen	Datum
*	Datenblatt	DS90CR218A 3.3VRising Edge Data Strobe LVDS 21Bit Chan Link 12MHz to 85MHz datasheet (Rev. D)		22.04.2013
	Anwendungshinweis	High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs		09.11.2018
	Anwendungshinweis	Receiver Skew Margin for Channel Link I and FPD Link I Devices	PDF \| HTML	13.01.2016
	Anwendungshinweis	AN-1538 Interfacing Nationals DS90CR218A and LM98714 (Rev. C)		26.04.2013
	Designleitfaden	Channel Link I Design Guide		29.03.2007
	Anwendungshinweis	Multi-Drop Channel-Link Operation		04.10.2004
	Anwendungshinweis	CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications		05.10.1998

Design und Entwicklung

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Simulationsmodell

DS90CR218A IBIS Model

SNLM058.ZIP (5 KB) - IBIS-Modell

Unterstützte Produkte und Hardware

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Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
TSSOP (DGG)	48	Ultra Librarian

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DS90CR218A

21-Bit Channel-Link-LVDS-Empfänger, +3,3V Rising Edge Data Strobe – 85 MHz

DS90CR218A

Produktdetails

Technische Dokumentation

Design und Entwicklung

DS90CR218A IBIS Model

Bestellen & Qualität

Support und Schulungen

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