LMH0340

AKTIV

Serializer und Treiber für 3G HD/SD, DVB-ASI SDI mit DLVDS-Schnittstelle

Produktdetails

Function Serializer Power consumption (mW) 475 Data rate (max) (Mbps) 2970 Control interface Pin/SMBus Operating temperature range (°C) -40 to 85
Function Serializer Power consumption (mW) 475 Data rate (max) (Mbps) 2970 Control interface Pin/SMBus Operating temperature range (°C) -40 to 85
WQFN (RHS) 48 49 mm² (7 mm × 7 mm)
  • LVDS Interface to Host FPGA
  • No External VCO or Clock Ref Required
  • Integrated Variable Output Cable Driver
  • 3.3V SMBus Configuration Interface
  • Integrated TXCLK PLL Cleans Clock Noise
  • Small 48-Pin WQFN Package
  • Industrial Temperature range: -40°C to 85°C

Key Specifications

  • Output Compliant With SMPTE 424M, SMPTE 292M, SMPTE 259M-C and DVB-ASI
  • Typical Power Dissipation: 440 mW
  • 30 ps Typical Output Jitter (HD, 3G)

All trademarks are the property of their respective owners.

  • LVDS Interface to Host FPGA
  • No External VCO or Clock Ref Required
  • Integrated Variable Output Cable Driver
  • 3.3V SMBus Configuration Interface
  • Integrated TXCLK PLL Cleans Clock Noise
  • Small 48-Pin WQFN Package
  • Industrial Temperature range: -40°C to 85°C

Key Specifications

  • Output Compliant With SMPTE 424M, SMPTE 292M, SMPTE 259M-C and DVB-ASI
  • Typical Power Dissipation: 440 mW
  • 30 ps Typical Output Jitter (HD, 3G)

All trademarks are the property of their respective owners.

The LMH0340/0040/0070/0050 SDI Serializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. An FPGA Host will format data with supplied IP such that the output of the LMH0340 is compliant with the requirements of DVB-ASI, SMPTE 259M-C, SMPTE 292M and SMPTE 424M standards. See for details on which Standards are supported per device.

The interface between the SER (Serializer) and the FPGA consists of a 5 bit wide LVDS data bus, an LVDS clock and an SMBus interface. The LMH0340/0040/0070 SER devices include an integrated cable driver which is fully compliant with all of the SMPTE specifications listed above. The LMH0050 has a CML output driver that can drive a differential transmission line or interface to a cable driver.

The FPGA-Attach SER/DES family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The SER is packaged in a physically small 48-pin WQFN package.

The LMH0340/0040/0070/0050 SDI Serializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. An FPGA Host will format data with supplied IP such that the output of the LMH0340 is compliant with the requirements of DVB-ASI, SMPTE 259M-C, SMPTE 292M and SMPTE 424M standards. See for details on which Standards are supported per device.

The interface between the SER (Serializer) and the FPGA consists of a 5 bit wide LVDS data bus, an LVDS clock and an SMBus interface. The LMH0340/0040/0070 SER devices include an integrated cable driver which is fully compliant with all of the SMPTE specifications listed above. The LMH0050 has a CML output driver that can drive a differential transmission line or interface to a cable driver.

The FPGA-Attach SER/DES family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The SER is packaged in a physically small 48-pin WQFN package.

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Technische Dokumentation

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Alle anzeigen 14
Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt LMH0340/040/070/050 3Gbps, HD, SD, DVB-ASI SDI Serializr & Cable Drvr w/LVDS I/F datasheet (Rev. I) 16.04.2013
Auswahlhilfe Broadcast and Professional Video Interface Solutions (Rev. E) PDF | HTML 05.04.2017
Anwendungshinweis AN-1972 Board Layout Challenges in Serial Digital Interface (Rev. C) 26.04.2013
Anwendungshinweis AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) 26.04.2013
Anwendungshinweis Triple Rate SDI IP FPGA Resource Utilization on SDXILEVK/AES-EXP-SDI-G Ref Dsgn (Rev. A) 26.04.2013
Anwendungshinweis AN-1988 LMH0340 / LMH0341 SerDes Family LVDS Timing Overview (Rev. A) 26.04.2013
Anwendungshinweis AN-2145 Power Considerations for SDI Products (Rev. B) 26.04.2013
Anwendungshinweis AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) 26.04.2013
Benutzerhandbuch SDALTEVK HSMC SDI Adapter board 05.03.2012
Benutzerhandbuch Triple-Rate SDI and Video Clocking Daughter Card 26.01.2012
Anwendungshinweis High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems 12.11.2009
Anwendungshinweis DS25CP104 in 3G SDI Router Application 20.08.2008
Anwendungshinweis A 3 Gbps SDI Connectivity Solution Supporting Uncompressed 1080p60 Video 18.03.2008
Designleitfaden Broadcast Video Owner's Manual 17.11.2006

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Codebeispiel oder Demo

BROADCAST_VIDEO_SERDES_IP — Broadcast-Video-Support-Code für LVDS-Schnittstelle-SDI-SerDes

We have developed a family of serializers and deserializers intended to support the serial digital interface (SDI) standards of the Society of Motion Picture and Television Engineers (SMPTE). These devices connect to a host FPGA through a moderate speed, moderate width (600 Mbps, 5 bits wide) (...)

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