SN65DSI83

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Einzelkanal-MIPI® DSI zu Single-Link-LVDS-Brücke und Flatlink™, integrierter Schaltkreis

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Datenblatt

document-pdfAcrobat SN65DSI83 MIPI DSI Bridge to FLAT LINK LVDS Single Channel DSI to SL LVDS Bridge datasheet (Rev. I) (Englisch) PDF | HTML

SN65DSI83

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Type

Bridge

Protocols

LVDS, MIPI DSI

Rating

Catalog

Speed (max) (Gbpp)

4

Operating temperature range (°C)

-40 to 85

Type

Bridge

Protocols

LVDS, MIPI DSI

Rating

Catalog

Speed (max) (Gbpp)

4

Operating temperature range (°C)

-40 to 85

NFBGA (ZXH)

64

25 mm² (5 mm × 5 mm)

Implements MIPI D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
Single channel DSI receiver configurable for 1, 2, 3, or 4 D-PHY data lanes per channel operating up to 1 Gbps/lane
Supports 18 bpp and 24 bpp DSI video packets with RGB666 and RGB888 formats
Max resolution up to 60 fps WUXGA 1920 × 1200 at 18 bpp and 24 bpp color with reduced blanking. suitable for 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp
FlatLink™ output for single-link LVDS
Supports single channel DSI to single-link LVDS operating mode
LVDS Output Clock Range of 25 MHz to 154 MHz
LVDS pixel clock may be sourced from free-running continuous D-PHY clock or external reference clock (REFCLK)
1.8-V main V_CC power supply
Low power features include shutdown mode, reduced LVDS output voltage swing, common mode, and MIPI ultra-low power state (ULPS) support
LVDS channel swap, LVDS PIN order reverse feature for ease of PCB routing
ESD rating ±2 kV (HBM)
Packaged in 64-pin 5-mm × 5-mm nFBGA (ZXH)
Temperature range: –40°C to 85°C

Implements MIPI D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
Single channel DSI receiver configurable for 1, 2, 3, or 4 D-PHY data lanes per channel operating up to 1 Gbps/lane
Supports 18 bpp and 24 bpp DSI video packets with RGB666 and RGB888 formats
Max resolution up to 60 fps WUXGA 1920 × 1200 at 18 bpp and 24 bpp color with reduced blanking. suitable for 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp
FlatLink™ output for single-link LVDS
Supports single channel DSI to single-link LVDS operating mode
LVDS Output Clock Range of 25 MHz to 154 MHz
LVDS pixel clock may be sourced from free-running continuous D-PHY clock or external reference clock (REFCLK)
1.8-V main V_CC power supply
Low power features include shutdown mode, reduced LVDS output voltage swing, common mode, and MIPI ultra-low power state (ULPS) support
LVDS channel swap, LVDS PIN order reverse feature for ease of PCB routing
ESD rating ±2 kV (HBM)
Packaged in 64-pin 5-mm × 5-mm nFBGA (ZXH)
Temperature range: –40°C to 85°C

The SN65DSI83 DSI to FlatLink bridge device features a single-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18 bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink-compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Single-Link LVDS with four data lanes per link.

The SN65DSI83 device can support up to WUXGA 1920 × 1200 at 60 frames per second, at 24 bpp with reduced blanking. The SN65DSI83 device is also suitable for applications using 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry-compliant interface technology, the SN65DSI83 device is compatible with a wide range of microprocessors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI defined ultra-low power state (ULPS) support.

The SN65DSI83 device is implemented in a small outline 5-mm × 5-mm nFBGA at 0.5-mm pitch package, and operates across a temperature range from –40°C to 85°C.

The SN65DSI83 DSI to FlatLink bridge device features a single-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18 bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink-compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Single-Link LVDS with four data lanes per link.

The SN65DSI83 device can support up to WUXGA 1920 × 1200 at 60 frames per second, at 24 bpp with reduced blanking. The SN65DSI83 device is also suitable for applications using 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry-compliant interface technology, the SN65DSI83 device is compatible with a wide range of microprocessors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI defined ultra-low power state (ULPS) support.

The SN65DSI83 device is implemented in a small outline 5-mm × 5-mm nFBGA at 0.5-mm pitch package, and operates across a temperature range from –40°C to 85°C.

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Technische Dokumentation

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Top-Dokumentation	Typ	Titel	Format-Optionen	Datum
*	Datenblatt	SN65DSI83 MIPI DSI Bridge to FLAT LINK LVDS Single Channel DSI to SL LVDS Bridge datasheet (Rev. I)	PDF \| HTML	01.10.2020
	Benutzerhandbuch	HSSC MicroStar BGA Discontinued and Redesigned		03.11.2020
	Anwendungshinweis	Troubleshooting SN65DSI8x - Tips and Tricks		27.08.2018
	Anwendungshinweis	SN65DSI83, SN65DSI84, and SN65DSI85 Hardware Implementation Guide (Rev. A)		11.04.2013
	Anwendungshinweis	SN65DSI8x Video Configuration Guide and Configuration Tool Software Users Manual (Rev. B)		08.04.2013

Design und Entwicklung

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