SN74ALS561A

These binary counters are programmable and offer synchronous and asynchronous clearing as well as synchronous and asynchronous loading. All synchronous functions are executed on the positive-going edge of the clock.

The clear function is initiated by applying a low level to either asynchronous clear (ACLR\) or synchronous clear (SCLR\). ACLR\ (direct clear) overrides all other functions of the device, while SCLR\ overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by applying a low level to asynchronous load (ALOAD\) or by the combination of a low level at synchronous load (SLOAD\) and a positive-going clock transition. The counting function is enabled only when enable P (ENP), enable T (ENT), ACLR\, ALOAD\, SCLR\, and SLOAD\ are all high.

A high level at the output-enable () input forces the Q outputs into the high-impedance state, and a low level enables those outputs. Counting is independent of OE\. ENT is fed forward to enable the ripple-carry output (RCO) to produce a high-level pulse while the count is maximum (15). The clocked carry output (CCO) produces a high-level pulse for a duration equal to that of the low level of the clock when RCO is high and the counter is enabled (ENP and ENT are high); otherwise, CCO is low. CCO does not have the glitches commonly associated with a ripple-carry output. Cascading is normally accomplished by connecting RCO or CCO of the first counter to ENT of the next counter. However, for very high-speed counting, RCO should be used for cascading because CCO does not become active until the clock returns to the low level.

The SN54ALS561A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS561A is characterized for operation from 0°C to 70°C.