SN74AVC16722

A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical V_OL vs I_OL and V_OH vs I_OH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC^TM ) Circuitry Technology and Applications, literature number SCEA009.

This 22-bit flip-flop is operational at 1.2-V to 3.6-V V_CC, but is designed specifically for 1.65-V to 3.6-V V_CC operation.

The 22 flip-flops of the SN74AVC16722 are edge-triggered D-type flip-flops with clock-enable (CLKEN\) input. On the positive transition of the clock (CLK) input, the device stores data into the flip-flops if CLKEN\ is low. If CLKEN\ is high, no data is stored.

A buffered output-enable (OE\) input places the 22 outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74AVC16722 is characterized for operation from -40°C to 85°C.