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66AK2L06

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Sistema en chip (SoC) DSP+ARM Keystone II multinúcleo

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66AK2L06

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Detalles del producto

CPU 32-/64-bit PCIe 2 PCIe Gen2 Hardware accelerators Digital Front End, FFT Coprocessor Features 4 lanes JESD204B Operating system INTEGRITY, Linux, Neutrino, PrOS, Windows Embedded CE Security Cryptographic acceleration, Device attestation & anti-counterfeit, Secure boot Rating Catalog Operating temperature range (°C) -40 to 100
CPU 32-/64-bit PCIe 2 PCIe Gen2 Hardware accelerators Digital Front End, FFT Coprocessor Features 4 lanes JESD204B Operating system INTEGRITY, Linux, Neutrino, PrOS, Windows Embedded CE Security Cryptographic acceleration, Device attestation & anti-counterfeit, Secure boot Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (CMS) 900 625 mm² (25 mm × 25 mm)
  • Four TMS320C66x DSP Core Subsystems (C66x
    CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point
      DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2
        GHz
    • Memory
      • 32K Byte L1P Per CorePac
      • 32K Byte L1D PerCorePac
      • 1024K Byte Local L2 Per CorePac
  • ARM CorePac
    • Two ARM® Cortex®-A15 MPCore™ Processors
      at Up to 1.2 GHz
    • 1MB L2 Cache Memory Shared by Two ARM
      Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC for Low
      Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory Shared by Four DSP
      CorePacs and One ARM CorePac
    • Memory Protection Unit for Both MSM SRAM
      and DDR3_EMIF
  • On-chip Standalone RAM (OSR) - 1MB On-Chip
    SRAM for Additional Shared Memory
  • Hardware Coprocessors
    • Two Fast Fourier Transform Coprocessors
      • Support Up to 1200 Msps at FFT Size 1024
      • Support Max FFT Size 8192
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • Packet-Based DMA for Zero-Overhead
      Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security AcceleratorEngine Enables Support for
      • IPSec, SRTP, and SSL/TLS Security
      • ECB, CBC, CTR, F8,CCM, GCM, HMAC,
        CMAC, GMAC, AES, DES, 3DES, SHA-1,
        SHA-2 (256-bit Hash), MD5
      • Up to 6.4 Gbps IPSec
    • Ethernet Subsystem
    • Peripherals
      • DigitalFront End (DFE) Subsystem
        • Support up to Four Lane JESD204A/B (7.37
          Gbps Line Rate Max.) Interface to Multiple
          Data Converters
        • Integration of Digital Down/Up-Conversion
          (DDC/DUC) Module
      • IQNet Subsystem
        • Transporting data streams to an integrated
          Digital Front End (DFE)
      • Two One-Lane PCIe Gen2 Interfaces
        • Supports Up to 5 GBaud
      • Three Enhanced Direct Memory Access (EDMA)
        Controllers
      • 72-Bit DDR3 Interface, Speeds Up to 1600 MHz
      • EMIF16 Interface
      • USB 3.0 Interface
      • USIM Interface
      • Four UART Interfaces
      • Three I2C Interfaces
      • 64 GPIO Pins
      • Three SPI Interfaces
      • Semaphore Module
      • Fourteen 64-Bit Timers
    • Commercial Case Temperature:
      • 0°C to 100°C
    • Extended Case Temperature:
      • –40°C to 100°C
  • Four TMS320C66x DSP Core Subsystems (C66x
    CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point
      DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2
        GHz
    • Memory
      • 32K Byte L1P Per CorePac
      • 32K Byte L1D PerCorePac
      • 1024K Byte Local L2 Per CorePac
  • ARM CorePac
    • Two ARM® Cortex®-A15 MPCore™ Processors
      at Up to 1.2 GHz
    • 1MB L2 Cache Memory Shared by Two ARM
      Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC for Low
      Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory Shared by Four DSP
      CorePacs and One ARM CorePac
    • Memory Protection Unit for Both MSM SRAM
      and DDR3_EMIF
  • On-chip Standalone RAM (OSR) - 1MB On-Chip
    SRAM for Additional Shared Memory
  • Hardware Coprocessors
    • Two Fast Fourier Transform Coprocessors
      • Support Up to 1200 Msps at FFT Size 1024
      • Support Max FFT Size 8192
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • Packet-Based DMA for Zero-Overhead
      Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security AcceleratorEngine Enables Support for
      • IPSec, SRTP, and SSL/TLS Security
      • ECB, CBC, CTR, F8,CCM, GCM, HMAC,
        CMAC, GMAC, AES, DES, 3DES, SHA-1,
        SHA-2 (256-bit Hash), MD5
      • Up to 6.4 Gbps IPSec
    • Ethernet Subsystem
    • Peripherals
      • DigitalFront End (DFE) Subsystem
        • Support up to Four Lane JESD204A/B (7.37
          Gbps Line Rate Max.) Interface to Multiple
          Data Converters
        • Integration of Digital Down/Up-Conversion
          (DDC/DUC) Module
      • IQNet Subsystem
        • Transporting data streams to an integrated
          Digital Front End (DFE)
      • Two One-Lane PCIe Gen2 Interfaces
        • Supports Up to 5 GBaud
      • Three Enhanced Direct Memory Access (EDMA)
        Controllers
      • 72-Bit DDR3 Interface, Speeds Up to 1600 MHz
      • EMIF16 Interface
      • USB 3.0 Interface
      • USIM Interface
      • Four UART Interfaces
      • Three I2C Interfaces
      • 64 GPIO Pins
      • Three SPI Interfaces
      • Semaphore Module
      • Fourteen 64-Bit Timers
    • Commercial Case Temperature:
      • 0°C to 100°C
    • Extended Case Temperature:
      • –40°C to 100°C

The 66AK2L06 KeyStone SoC is a member of the C66x family based on TI's new KeyStone II Multicore SoC Architecture and is a low-power solution with integrated JESD204B lanes that meets the more stringent power, size, and cost requirements of applications requiring connectivity with ADC and DAC based applications. The device’s ARM and DSP cores deliver exceptional processing power on platforms requiring high signal and control processing.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM CorePac, C66x CorePacs, IP network, Digital Front End, and FFT processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The addition of the ARM CorePac in the 66AK2L06 device enables the ability for complex control code processing on-chip. Operations such as housekeeping and management processing can be performed with the Cortex-A15 processor.

TI’s new C66x core launches a new era of DSP technology by combining fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x CorePac incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2L06 contains many coprocessors to offload the bulk of the processing demands of higher layers of application. This keeps the cores free for algorithms and other differentiating functions. The SoC contains multiple copies of key coprocessors such as the FFTC. The architectural elements of the SoC (Multicore Navigator) ensure that data is processed without any CPU intervention or overhead, allowing the system to make optimal use of its resources.

TI’s scalable multicore SoC architecture solutions provide developers with a range of software-compatible and hardware-compatible devices to minimize development time and maximize reuse.

The 66AK2L06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows and Linux debugger interface for visibility into source code execution.

The 66AK2L06 KeyStone SoC is a member of the C66x family based on TI's new KeyStone II Multicore SoC Architecture and is a low-power solution with integrated JESD204B lanes that meets the more stringent power, size, and cost requirements of applications requiring connectivity with ADC and DAC based applications. The device’s ARM and DSP cores deliver exceptional processing power on platforms requiring high signal and control processing.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM CorePac, C66x CorePacs, IP network, Digital Front End, and FFT processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The addition of the ARM CorePac in the 66AK2L06 device enables the ability for complex control code processing on-chip. Operations such as housekeeping and management processing can be performed with the Cortex-A15 processor.

TI’s new C66x core launches a new era of DSP technology by combining fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x CorePac incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2L06 contains many coprocessors to offload the bulk of the processing demands of higher layers of application. This keeps the cores free for algorithms and other differentiating functions. The SoC contains multiple copies of key coprocessors such as the FFTC. The architectural elements of the SoC (Multicore Navigator) ensure that data is processed without any CPU intervention or overhead, allowing the system to make optimal use of its resources.

TI’s scalable multicore SoC architecture solutions provide developers with a range of software-compatible and hardware-compatible devices to minimize development time and maximize reuse.

The 66AK2L06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows and Linux debugger interface for visibility into source code execution.
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos 66AK2L06 Multicore DSP+ARM KeyStone II System-on-Chip (SoC) datasheet 21/04/2015
* Errata 66AK2Lxx Multicore DSP+ARM KeyStone II SOC (Silicon Revision 1.0) 20/04/2015
Nota sobre la aplicación DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 7/07/2022
Nota sobre la aplicación Keystone Error Detection and Correction EDC ECC (Rev. A) 25/06/2021
Nota sobre la aplicación Using Arm ROM Bootloader on Keystone II Devices PDF | HTML 4/06/2019
Guía del usuario KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) 21/08/2017
Nota sobre la aplicación Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 14/08/2017
Guía del usuario Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 26/07/2017
Guía de diseño Wideband Receiver With 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design 23/09/2016
Nota sobre la aplicación Keystone EDMA FAQ 1/09/2016
Third party document XEVMK2LX Quick Setup Guide 3/08/2016
Third party document Download XEVMK2LX schematics, bill of materials and design guide 3/08/2016
Guía del usuario Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) 27/07/2016
Nota sobre la aplicación Power Management of KS2 Device (Rev. C) 15/07/2016
Nota sobre la aplicación 66AK2L06 JESD Attach to ADC12J4000/DAC38J84 Getting Started Guide (Rev. B) 20/06/2016
Artículo técnico How to complete your RF sampling solution PDF | HTML 18/05/2016
Nota sobre la aplicación SERDES Link Commissioning on KeyStone I and II Devices 13/04/2016
Artículo técnico Accelerating the Fast Fourier Transform (FFT/iFFT) by 10x and more PDF | HTML 2/03/2016
Informe Multicore SoCs stay a step ahead of SoC FPGAs 23/02/2016
Nota sobre la aplicación TI DSP Benchmarking PDF | HTML 13/01/2016
Nota sobre la aplicación Throughput Performance Guide for KeyStone II Devices (Rev. B) 22/12/2015
Informe Optimizing Modern Radar Systems using Low- Latency, High-Performance FFT Coproce 17/12/2015
Artículo técnico Are 66AK2L06 SoCs an answer to miniaturization of test and measurement equipment? PDF | HTML 2/12/2015
Informe Optimizing your test and measurement solution by leveraging the most integrated 3/11/2015
Guía de diseño 66AK2L06 JESD Attach to ADC12J4000 / DAC38J84 Design Guide (Rev. A) 22/10/2015
Nota sobre la aplicación Keystone II DDR3 Debug Guide 16/10/2015
Nota sobre la aplicación System solution for avionics & defense 23/09/2015
Nota sobre la aplicación TPS544Bxx/TPS544Cxx Powering TCI6630K2L in Smart Reflex Class 0 TC Mode 18/09/2015
Artículo técnico Summertime showdown: DSPs vs FPGAs PDF | HTML 9/07/2015
Guía del usuario Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) PDF | HTML 6/05/2015
Artículo técnico Wireless infrastructure - Now simpler and more accessible! PDF | HTML 5/05/2015
Guía del usuario Gigabit Ethernet (GbE) Switch SS for K2E & K2L Devices User's Guide (Rev. A) 28/04/2015
Product overview 66AK2L06 SoC Product Bulletin 15/04/2015
Guía del usuario Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 9/04/2015
Informe Optimizing synthetic aperture radar design with TI's integrated 66AK2L06 SoC 9/04/2015
Guía del usuario DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) 27/03/2015
Guía del usuario Digital Front End (DFE) for Keystone II Devices User's Guide (Rev. A) 23/03/2015
Informe Ready to make the jump to JESD204B? White Paper (Rev. B) 19/03/2015
Guía del usuario Fast Fourier Transform Coprocessor (FFTC) for KeyStone II Devices User's Guide (Rev. A) 11/02/2015
Nota sobre la aplicación Keystone II DDR3 Initialization 26/01/2015
Guía del usuario IQN2 for KeyStone II Devices User's Guide (Rev. A) 1/10/2014
Guía del usuario Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 4/09/2014
Guía del usuario Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide 19/08/2014
Guía del usuario Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide 19/08/2014
Guía del usuario Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide 13/08/2014
Nota sobre la aplicación Hardware Design Guide for KeyStone II Devices 24/03/2014
Guía del usuario Debug and Trace for KeyStone II Devices User's Guide 26/07/2013
Guía del usuario DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) 15/07/2013
Guía del usuario Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 28/06/2013
Guía del usuario C66x CorePac User's Guide (Rev. C) 28/06/2013
Guía del usuario Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices 12/11/2012
Guía del usuario ARM CorePac User Guide for KeyStone II Devices 31/10/2012
Nota sobre la aplicación Multicore Programming Guide (Rev. B) 29/08/2012
Guía del usuario Semaphore2 Hardware Module for KeyStone Devices User's Guide (Rev. A) 24/04/2012
Guía del usuario Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 30/03/2012
Guía del usuario Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 27/03/2012
Guía del usuario 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 22/03/2012
Nota sobre la aplicación PCIe Use Cases for KeyStone Devices 13/12/2011
Nota sobre la aplicación Introduction to TMS320C6000 DSP Optimization 6/10/2011
Guía del usuario Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 2/09/2011
Guía del usuario External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 24/05/2011
Informe Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 19/05/2011
Nota sobre la aplicación Optimizing Loops on the C66x DSP 9/11/2010
Guía del usuario General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 9/11/2010
Guía del usuario C66x CPU and Instruction Set Reference Guide 9/11/2010
Nota sobre la aplicación Clocking Design Guide for KeyStone Devices 9/11/2010
Guía del usuario C66x DSP Cache User's Guide 9/11/2010

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Sonda de depuración

TMDSEMU200-U — Sonda de depuración XDS200 USB

El XDS200 es una sonda de depuración (emulador) que se utiliza para depurar dispositivos integrados de TI. Para la mayoría de los dispositivos, se recomienda utilizar el XDS110 (www.ti.com/tool/TMDSEMU110-U), que es más nuevo y de menor costo. El XDS200 es compatible con una amplia variedad de (...)

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Sonda de depuración

TMDSEMU560V2STM-U — Sonda de depuración USB para rastreo del sistema con el software XDS560™ v2

El XDS560v2 es el modelo de mayor rendimiento de la familia de sondas de depuración XDS560™ y es compatible tanto con el estándar JTAG tradicional (IEEE 1149.1) como con cJTAG (IEEE 1149.7).  Tenga en cuenta que no es compatible con la depuración por cable serie (SWD).

Todas las sondas de (...)

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Sonda de depuración

TMDSEMU560V2STM-UE — Sonda de depuración USB y ethernet de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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Sonda de depuración

LB-3P-TRACE32-DSP — Sistema de depuración y seguimiento Lauterbach TRACE32 para procesadores de señales digitales (DSP)

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

Desde: Lauterbach GmbH
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Kit de desarrollo de software (SDK)

BIOSLINUXMCSDK-K2 — MCSDK supporting SYS/BIOS RTOS and Linux OS for KeyStone II ARM A15 + DSP C66x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

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Kit de desarrollo de software (SDK)

PROCESSOR-SDK-LINUX-K2L — Linux Processor SDK for K2L

El procesador de kit de desarrollo de software (SDK) es una plataforma de software unificada para procesadores integrados de TI que ofrece una configuración sencilla y un rápido acceso inmediato a pruebas de rendimiento y demostraciones.  Todas las versiones del SDK del procesador son coherentes (...)

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PROCESSOR-SDK-LINUX-RT-K2L — Linux-RT Processor SDK for K2L

El procesador de kit de desarrollo de software (SDK) es una plataforma de software unificada para procesadores integrados de TI que ofrece una configuración sencilla y un rápido acceso inmediato a pruebas de rendimiento y demostraciones.  Todas las versiones del SDK del procesador son coherentes (...)

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Kit de desarrollo de software (SDK)

PROCESSOR-SDK-RTOS-K2L — RTOS Processor SDK for K2L

El procesador de kit de desarrollo de software (SDK) es una plataforma de software unificada para procesadores integrados de TI que ofrece una configuración sencilla y un rápido acceso inmediato a pruebas de rendimiento y demostraciones.  Todas las versiones del SDK del procesador son coherentes (...)

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Kit de desarrollo de software (SDK)

RFSDK — Kit de desarrollo de software de radiofrecuencia (RFSDK)

Texas Instruments Radio Frequency Software Development Kit (RFSDK) is a collection of highly optimized APIs and highly abstracted commands to control, configure and manage the JESD204B interface, digital front end (DFE), analog front end (AFE) and high speed data converters (ADC/DAC). The RFSDK (...)

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IDE, configuración, compilador o depurador

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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Controlador o biblioteca

MATHLIB — Biblioteca matemática DSP para dispositivos de punto flotante

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
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SPRC264 — TMS320C5000/6000 Biblioteca de imágenes (IMGLIB)

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SPRC265 — Biblioteca DSP TMS320C6000 (DSPLIB)

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Códec de software

C66XCODECS — CÓDECS (video, voz) para dispositivos basados en C66x

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Modelo de simulación

66AK2L06 Power Consumption Model

SPRM656.ZIP (169 KB) - Modelo de potencia
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lock = Requiere aprobación de exportación (1 minuto)
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Diseño de referencia

TIDEP0034 — Procesador 66AK2L06 DSP+ARM con conexión de JESD204B a ADC y DAC de banda ancha

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TIDEP0060 — Diseño de referencia de sistema de radar optimizado con un DSP+ARM SoC

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Diseño de referencia

TIDEP0081 — Diseño de referencia de diseño de receptor de banda ancha con conexión de 66AK2L06 JESD204B a ADC32R

Para desarrolladores de sistemas receptores de banda ancha que actualmente utilizan FPGA o ASIC para conectar convertidores de datos de alta velocidad a un procesador de banda base, que necesitan una comercialización más rápida con un mayor rendimiento y una reducción significativa de costos, (...)
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FCBGA (CMS) 900 Ultra Librarian
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