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DRV3263-Q1

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Controlador de compuerta automotriz trifásico para baterías de 48 V, detección precisa de corriente

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Hoja de datos

DRV3263-Q1

PRESENTACIÓN PRELIMINAR
Hoja de datos Haga su pedido ahora

Detalles del producto

Rating Automotive Architecture Gate driver Control interface 1xPWM, 3xPWM, 6xPWM, SPI Gate drive (A) 1 Vs (min) (V) 8 Vs ABS (max) (V) 85 Features (x1) PWM, (x3) PWM, Current sense Amplifier, SPI/I2C, Watchdog timer Operating temperature range (°C) -40 to 150 TI functional safety category Functional Safety-Compliant
Rating Automotive Architecture Gate driver Control interface 1xPWM, 3xPWM, 6xPWM, SPI Gate drive (A) 1 Vs (min) (V) 8 Vs ABS (max) (V) 85 Features (x1) PWM, (x3) PWM, Current sense Amplifier, SPI/I2C, Watchdog timer Operating temperature range (°C) -40 to 150 TI functional safety category Functional Safety-Compliant
VQFN (RGZ) 48 49 mm² (7 mm × 7 mm)
  • AEC-Q100 Test Guidance for automotive applications
    • Device ambient temperature: –40°C to +150°C
  • Functional Safety-Compliant
    • Developed for functional safety applications
    • Documentation to aid ISO 26262 system design will be available upon production release
    • Systematic capability up to ASIL D targeted
  • Three phase half-bridge gate driver
    • Drives six N-channel MOSFETs (NMOS)
    • 8 to 85V wide operating voltage range
    • Bootstrap architecture for high-side gate driver
    • 50mA average gate switching current enables driving 400nC MOSFETs at 20kHz
    • Trickle charge pump to support 100% PWM duty cycle and to generate overdrive supply
  • Cutoff driver
    • Drive N-channel MOSFET cutoff switches in multiple topologies
    • Two SPI-controllable channels (DRV3263A) or
    • One channel with SPI or HW pin control (DRV3263B)
  • Smart Gate Drive architecture
    • 15-level configurable peak gate drive current up to 1000 / 2000mA (source / sink)
    • Independently configurable pre-charge and pre-discharge regions
    • Configurable soft shutdown to minimize inductive voltage spikes during overcurrent shutdown
  • Low-side Current Sense Amplifier
    • Sub-1mV low input offset across temperature
    • 8-level adjustable gain
  • SPI-based detailed configuration and diagnostics with OTP memory to store default configuration settings
  • DRVOFF independent driver disable pin
  • High voltage wake up pin (nSLEEP)
  • 6x, 3x, 1x, and Independent PWM modes
  • Supports 3.3V and 5V logic inputs
  • Integrated protection features
    • Battery and power supply voltage monitors
    • MOSFET VDS and Rsense over current monitors
    • MOSFET VGS gate fault monitors
    • Analog Built-In Self-Test (ABIST)
    • Device thermal warning and shutdown
    • Fault condition indicator pin
  • AEC-Q100 Test Guidance for automotive applications
    • Device ambient temperature: –40°C to +150°C
  • Functional Safety-Compliant
    • Developed for functional safety applications
    • Documentation to aid ISO 26262 system design will be available upon production release
    • Systematic capability up to ASIL D targeted
  • Three phase half-bridge gate driver
    • Drives six N-channel MOSFETs (NMOS)
    • 8 to 85V wide operating voltage range
    • Bootstrap architecture for high-side gate driver
    • 50mA average gate switching current enables driving 400nC MOSFETs at 20kHz
    • Trickle charge pump to support 100% PWM duty cycle and to generate overdrive supply
  • Cutoff driver
    • Drive N-channel MOSFET cutoff switches in multiple topologies
    • Two SPI-controllable channels (DRV3263A) or
    • One channel with SPI or HW pin control (DRV3263B)
  • Smart Gate Drive architecture
    • 15-level configurable peak gate drive current up to 1000 / 2000mA (source / sink)
    • Independently configurable pre-charge and pre-discharge regions
    • Configurable soft shutdown to minimize inductive voltage spikes during overcurrent shutdown
  • Low-side Current Sense Amplifier
    • Sub-1mV low input offset across temperature
    • 8-level adjustable gain
  • SPI-based detailed configuration and diagnostics with OTP memory to store default configuration settings
  • DRVOFF independent driver disable pin
  • High voltage wake up pin (nSLEEP)
  • 6x, 3x, 1x, and Independent PWM modes
  • Supports 3.3V and 5V logic inputs
  • Integrated protection features
    • Battery and power supply voltage monitors
    • MOSFET VDS and Rsense over current monitors
    • MOSFET VGS gate fault monitors
    • Analog Built-In Self-Test (ABIST)
    • Device thermal warning and shutdown
    • Fault condition indicator pin

The DRV3263-Q1 is an integrated smart gate driver for 48V automotive three-phase BLDC applications. The device provides three half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The DRV3263-Q1 generates the correct gate drive voltages using an external 12V supply and an integrated bootstrap diode for the high-side MOSFETs. A trickle charge pump allows for the gate drivers to support 100% PWM duty cycle control and provides overdrive gate drive voltage for driving external switches, which can be controlled through dedicated cutoff driver pins.

The DRV3263-Q1 provides low-side current sense amplifiers to support resistor based low-side current sensing. The low offset and low gain error of the amplifiers enable the system to obtain precise motor current measurements.

A wide range of diagnostics and protection features are integrated with the DRV3263-Q1, enabling a robust motor drive system design and reduce external components. The highly configurable device response allows the device to be integrated seamlessly into a variety of system designs.

The DRV3263-Q1 is an integrated smart gate driver for 48V automotive three-phase BLDC applications. The device provides three half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The DRV3263-Q1 generates the correct gate drive voltages using an external 12V supply and an integrated bootstrap diode for the high-side MOSFETs. A trickle charge pump allows for the gate drivers to support 100% PWM duty cycle control and provides overdrive gate drive voltage for driving external switches, which can be controlled through dedicated cutoff driver pins.

The DRV3263-Q1 provides low-side current sense amplifiers to support resistor based low-side current sensing. The low offset and low gain error of the amplifiers enable the system to obtain precise motor current measurements.

A wide range of diagnostics and protection features are integrated with the DRV3263-Q1, enabling a robust motor drive system design and reduce external components. The highly configurable device response allows the device to be integrated seamlessly into a variety of system designs.
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* Hoja de datos DRV3263-Q1 48V Battery 3-Phase Gate Driver Unit with Integrated Cutoff Drivers datasheet PDF | HTML 26/03/2026

Diseño y desarrollo

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Placa de evaluación

DRV8363-Q1EVM — Módulo de evaluación DRV8363-Q1

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El EVM permite evaluar rápidamente el dispositivo DRV8363-Q1, que hace girar un motor BLDC con conmutación y control trapezoidales.

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Herramienta de diseño

DRV3263-Q1-DESIGN-TOOL — DRV3263-Q1-DESIGN documentation

Documentation and tools for DRV3263 design support
Productos y hardware compatibles
Herramienta de diseño

DRV3263-Q1-SAFETY-DOCS-DESIGN-TOOL — DRV3263-Q1 functional safety documents

DRV3263_Safety_Manual
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Diseño de referencia

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El freno electromecánico (EMB) es un nuevo tipo de tecnología de frenado destinada a la electrificación y la inteligencia de los automóviles; proporciona un ahorro general de costos, una respuesta más rápida y un funcionamiento más preciso para una conducción autónoma avanzada. Este diseño de (...)

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