DS90CR288A

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Receptor Channel Link LVDS de +3.3 V, 28 bits, 85 MHz y flanco de subida con luz estroboscópica de d

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Hoja de datos

document-pdfAcrobat DS90CR287/DS90CR288A 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link 85MHz datasheet (Rev. G) (Inglés)

DS90CR288A

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Detalles del producto

Protocols

Catalog

Rating

Catalog

Operating temperature range (°C)

-10 to 70

Protocols

Catalog

Rating

Catalog

Operating temperature range (°C)

-10 to 70

TSSOP (DGG)

56

113.4 mm² (14 mm × 8.1 mm)

20 to 85 MHz Shift Clock Support
50% Duty Cycle on Receiver Output Clock
2.5 / 0 ns Set & Hold Times on TxINPUTs
Low Power Consumption
±1V Common-Mode Range (around +1.2V)
Narrow Bus Reduces Cable Size and Cost
Up to 2.38 Gbps Throughput
Up to 297.5 Mbytes/sec Bandwidth
345 mV (typ) Swing LVDS Devices for Low EMI
PLL Requires no External Components
Rising Edge Data Strobe
Compatible with TIA/EIA-644 LVDS Standard
Low Profile 56-Lead TSSOP Package

20 to 85 MHz Shift Clock Support
50% Duty Cycle on Receiver Output Clock
2.5 / 0 ns Set & Hold Times on TxINPUTs
Low Power Consumption
±1V Common-Mode Range (around +1.2V)
Narrow Bus Reduces Cable Size and Cost
Up to 2.38 Gbps Throughput
Up to 297.5 Mbytes/sec Bandwidth
345 mV (typ) Swing LVDS Devices for Low EMI
PLL Requires no External Components
Rising Edge Data Strobe
Compatible with TIA/EIA-644 LVDS Standard
Low Profile 56-Lead TSSOP Package

The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.

The DS90CR288A receiver converts the four LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.

The DS90CR288A receiver converts the four LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

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Documentación técnica

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Documentación principal	Tipo	Título	Opciones de formato	Fecha
*	Hoja de datos	DS90CR287/DS90CR288A 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link 85MHz datasheet (Rev. G)		5/03/2013
	Nota sobre la aplicación	High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs		9/11/2018
	Nota sobre la aplicación	Receiver Skew Margin for Channel Link I and FPD Link I Devices	PDF \| HTML	13/01/2016
	Guía de diseño	Channel Link I Design Guide		29/03/2007
	Nota sobre la aplicación	Multi-Drop Channel-Link Operation		4/10/2004
	Nota sobre la aplicación	CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications		5/10/1998

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

FLINK3V8BT-85 — Kit de evaluación para la familia FPD-Link de dispositivos LVDS serializadores y deserializadores

The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.

The transmitter board accepts (...)

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