SN10KHT5574

ACTIVO

Traductor de ECL a TTL octales con biestables con activación de borde de tipo D y 3 salidas de estad

Detalles del producto

Technology family TTL Applications GTL Rating Catalog Operating temperature range (°C) 0 to 70
Technology family TTL Applications GTL Rating Catalog Operating temperature range (°C) 0 to 70
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • 10KH Compatible
  • ECL Clock and TTL Control Inputs
  • Flow-Through Architecture Optimizes PCB Layout
  • Center Pin VCC, VEE, and GND Configurations Minimize High-Speed Switching Noise
  • Package Options Include "Small Outline" Packages and Standard Plastic DIPs
  • 10KH Compatible
  • ECL Clock and TTL Control Inputs
  • Flow-Through Architecture Optimizes PCB Layout
  • Center Pin VCC, VEE, and GND Configurations Minimize High-Speed Switching Noise
  • Package Options Include "Small Outline" Packages and Standard Plastic DIPs

This octal ECL-to-TTL translator is designed to provide efficient translation between a 10KH ECL signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

The eight flip-flops of the SN10KHT5574 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic levels that were set up at the D inputs.

A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

The output-enable input OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are off.

The SN10KHT5574 is characterized for operation from 0°C to 75°C.

This octal ECL-to-TTL translator is designed to provide efficient translation between a 10KH ECL signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

The eight flip-flops of the SN10KHT5574 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic levels that were set up at the D inputs.

A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

The output-enable input OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are off.

The SN10KHT5574 is characterized for operation from 0°C to 75°C.

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Documentación técnica

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Tipo Título Fecha
* Data sheet Octal ECL-to-TTL Translator w/D-Type Edge-Triggered FF & 3-State Outputs datasheet 01 oct 1990

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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